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[SOLVED] How large is the dissipating ground plane on bottom layer of JESD51-7 test board

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ridgemao1983

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From the datasheet(**broken link removed**
Thermal Resistance (θJA) eMSOP10: 45°C/W.
All numbers apply for packages soldered directly on to a 3”x3” PC board with 2 oz.copper on 4 layers in still air.

I think the test board used to obtain 45°C/W complies with JESD51-7 standard.

How large is the dissipating ground plane on top and bottom layer of this test board?
Is it "No GND on top and bottom other than DAP landing" or "Maximize ground area for top and bottom layer" ?

I can't find any related statement in the JESD51-7, if you could, can you tell me where it is in the standard ?

Thanks.
 

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I don't think that the datasheet does refer particularly to the Jedec spec, except for the 3x3" dimension. TI e.g assumes 2 oz plane copper, JEDEC 1 oz. JEDEC specifies traces on top and bottom and no copper pour. It also doesn't account for thermal pads as it explicitely excludes thermal vias.
 

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