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synthesis...how to mark a gate as black box

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satishgra

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Hi,

I have a half adder and want a synthesized netlist out of it where in all the nand gates {for example} need to be considered as black boxes. I want to use the RC netlist directly in the final resulting netlist.

Basically, I am looking at using HSIM for co simulation and then use prime time to generate the power numbers. Unfortunately, for PT to run, it needs a synthesised netlist.

This is just a small example and I have a huge design where I want to implement the same procedure

Regards,
Satish
 

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