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Using correct libraries for vectors with 2s compliment no.

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neocool

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Using correct libraries

Hi again,
In the example below, if my vectors contain 2's compliment numbers, what libraries should I use to make the code execute correctly? I don't really care about whether to use TO_SIGNED or CONV_SIGNED. I am just confused when to use which library (std_numeric, std_logic_artith, std_logic_unsigned, std_logic_signed)?

Code: 
signal max: sd_logic_vector(9 downto 0);
signal a: sd_logic_vector(9 downto 0);
signal result: sd_logic_vector(10 downto 0);

result <= std_logic_vector(signed(max) - signed(a));

Using these libraries, the code has compiled:
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

But can I use STD_LOGIC_UNSIGNED in this context of 2's compliment arithmetic?
Should I use std_logic_arith? maybe std_logic_signed?
Can I use std_numeric with std_logic_arith?

Thank you
 

Re: Using correct libraries

For VHDL, depend on packages you declares, you can use types:
1. For unsigned:
- numeric_std package: use unsigned type
- std_logic_arith package: use unsigned type
- std_logic_unsigned package: use std_logic_vector
2. For signed:
- numeric_std package: use signed type
- std_logic_arith package: use signed type
- std_logic signed package: use std_logic_vector
 

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    neocool

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Using correct libraries

can I use std_logic_arith (signed and unsigned) and std_numeric (signed) libraries in the same module or it's better not to?

The reason I am asking that question is because I have signed addition and subtraction in a module, and ModelSim gives a good simulation result. However implementing it on hardware, gives some errors - the signal is cut and shifted as there was a confusion between signed and unsigned types inside. There, I am using std_numeric and 1164 libraries only. The compiler allows me to include std_logic_unsigned there as well, but it does not make a difference on either (software or hardware) simulations.



Thanks
 

Re: Using correct libraries

I think you only should use std_logic_arith or numeric_std package.
In your module, the problem may be:
- when you add signed numbers, overflow may occur. You must predict range of result to choose number of bit, i.e. a 8-bit number has a range of -128 to +127.
- If you don't want to overflow, you must do 1-bit sign extension. The result is always correct.
 

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    neocool

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Using correct libraries

thanks

So, which library does allow adding SLV and integer to get SLV (for counters)?

In my code, I am using resulting vector with length of one extra bit to account for overflow.
I.e. (10 downto 0) <= ('0' & (9 downto 0)) - ('1' & (9 downto 0));
assuming first number is positive and second is negative SLV represented in 2's compliment.
I don't know where the problem comes from as the simulation using Modelsim shows no errors, while hardware implementation does. When I am using another function that uses +ve/-ve variable results for calculations and converts them into signed SLV, both hardware and modelsim testing are good.

thank you again
 

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