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Does RESET signal need a buffer tree?

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monsoom

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I am reading the book "Reuse Methodology Manual for SOC Designs". It is mentioned in the book that a RESET signal needs a buffer tree just like the clock signal does. I think the RESET does need a buffer tree. But how? Did anyone have done the "RESET tree synthesis" or something like this in practical? Which EDA tools can do this job? I will be very thankful to known these. :)
 

I THINK IT REALY DEPENDS IF RESET IS SYNCHRONOUS OR ASYNCHRONOUS, AND HOW OFTEN IT IS USED - MOST RESETS ARE ASYNCHRONOUS, AND USED ONLY AT START - UP (POWER ON RESET) OR SELDOM (LIKE SOFTWARE RESET).

USUALLY A SIMPLE BUFFER IS NEEDED - JUST TO DRIVE A SUFFICIENT SIGNAL.
 

In most multi-clock domain systems, the fanout load for reset may be even larger than a clock tree and thus a buffer tree is needed.

Another point is if all flops are using a common async. reset using a small buffer, then it is very likely that these reset won't work since the total input capacitance is too large.

One final point about reset tree is the buffer skew and insertion delay requirement can be relaxed when compared with clock trees.
 

You just set dont_touch when doing synthesis as clk net. You can do high fan net tree when do backend.
 

I see. Thank you for all your answers! I will try.
 

monsoom said:
I am reading the book "Reuse Methodology Manual for SOC Designs". It is mentioned in the book that a RESET signal needs a buffer tree just like the clock signal does. I think the RESET does need a buffer tree. But how? Did anyone have done the "RESET tree synthesis" or something like this in practical? Which EDA tools can do this job? I will be very thankful to known these. :)
Click to expand...

Reset needs buffer trees of course because you need to initialize all internal registers' state, so the design can work after reset.

In apr tools, you jsut treat it as a high fanout net, then do the buffer tree insertion.

But you must check reset signal 's latency to each ffs.
 

in async reset condition, all dff need to be set to KOWN value at almost same time,so a buffer tree is needed . in multiple clock design may be each reset of relevent clock need reset sequence . buffer must be carefully make .
 

If the skew of the reset causes timing failure or the fanout is huge and exceed the maxium transition timing violation. I think you should make a buffer tree like CTS.
 

It's decided by your timing constraint, if fanout is so large then you shoud insert reset tree
 

backend tools can automatically deal with reset , eg socencounter.
 

"If the skew of the reset causes timing failure or the fanout is huge and exceed the maxium transition timing violation. I think you should make a buffer tree like CTS."
no problem occured or async reset when it is asserted, but more attention must be payed when reset is removed.
 

Hi,
What is the equilvalent command for the set dont touch in magma?
Regards
Vicky
 

Reset signal need a buffer tree, if no buffer tree, the signal trsition at the flop's

reset input will be very large, perhaps this will cause flop's operate incorrectly.




monsoom said:
I am reading the book "Reuse Methodology Manual for SOC Designs". It is mentioned in the book that a RESET signal needs a buffer tree just like the clock signal does. I think the RESET does need a buffer tree. But how? Did anyone have done the "RESET tree synthesis" or something like this in practical? Which EDA tools can do this job? I will be very thankful to known these. :)
Click to expand...
 

yes , reset is the same as clock,
tree is needed.
 

I don't think rst should be treated as clk.

A rst pin never flips as frequent as clk, and in pr tool, it was treated as a high fanout net and synthesized when HFS.

And of course the rst has a tree structure. This is determined by the load.
 

If you reset is asynchronous, and you have a close constrain on system reset time, buffer tree is inevitable, if the reset is synchronous, buffer tree is not essential.
 

This is from the analog side:

Most designs have a much higher fanin for reset than for clk. To avoid a reset tree you have to give up even to have the drive capability to toggle the reset with the clk. So how it works?

1. Use asyn FF
2. Disable the clk
3. Make reset active (it could take a number of clk)
4. Disable reset (also slow)
5. Start clk

Greetings from the analog world!
 

Astro can do this automatically. Just set_dont_touch_network rst_n
set_ideal_net rst_buf/Y
 

Yes itsi needed..

Reset must be done to all flipflops at same time in synchoronous design.. so you need tree.

If tree is not preset some flipflops go to reset while other in some logic.. all goes wrong after that...



Regards
Shankar
 

In asynchronous design, when reset is active, clock is not running. There is no necessary to balance reset same as clock tree. Only transition time should be meet.
 

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