MOS Transistor Area confusion !!??

calculate drain diffusion periphery

I have a small confusion regarding the area of the MOS transistor. When we use a MOS transistor for simulation in Cadence we set its properties through a property dialog box as shown in the attached image. In this dialog box we have the fields for the Source and Drain diffusion area as

0.7u*iPar("w")

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I understand that this means that the source and drain diffusion area lateral length is taken to be 0.7um and that will be multiplied by the transistor width to give the actual source/drain diffucion area.

My 1st question is how much difference does this 0.7um make on the simulation results. Suppose I change this to 1um, what type of changes should I expect in my results, which I obtained previously from 0.7um???

In the Source/Drain diffusion periphery dialog box it is written:

1.4u+2*iPar("w")

Click to expand...

I understand this as obvious formula for the perimeter. My problem is that someone told me that the periphery area is taken to be

1.4u+iPar("w")

Click to expand...

i.e. without the factor of 2. I don't see how or why??? If it is then why??? They say that the periphery bordering the channel is not considered???

Any views, suggestions comments would be really helpful !

The source/drain area is used to calculate capacitance. I'm guessing the 0.7 is the minimum ground rule for the distance between gates of the drain/source region. This is most likely the way the p-cell was generated. If you flaten the p-cell so you can change the layout you will need to modify the equations. I would talk to one of your cadence experts to verify how the equations are used and what parameters are passed to the simulator.

yes,it's used to calculate the caps of both sidewall and junctions.

But if the drain is shared by 2 two transistors on the layout (ABAB shape), your simulation will include the junction capacitor twice!
Anyway, 1.4u+2*iPAR("w") is the right input in most cases. :sm38: