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Tran violation on output pin of the cell

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kpsr

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Hi folks,

I am seeing transition violation on output pin of the cell even though input pin transition and output load is fine.

Input pin transition is good output pin load is small. I am seeing transition violation on output pin of the cell. I am not getting the reason for this issue

Can any one please tell me reason for this issue


Best Regard's,
kpsr
 

Hi vasaroopak,

For ever signal having transition period we will calculate cell delay based on input transition and output load.
we will put some transition limit for every pin if transition of signal is greater than our limit then we report the signal as a violated path.
 

Hi,

I cleared the violation by sizing cell, What I am not getting what is the reason for getting that tran violation on output pin
 

I suppose the max_tran limit is coming from the values specified in the .lib. So even though the output load looks small, you need to check what is the max value specified in the lib and perhaps your load exceeds this one, hence the violation.
 

3 possible causes (at least):

1. pin load was too large.
2. driving cell was too weak.
3. routing was bad (thin, detours) or too long.
 

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