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Verilog Shift Register

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TrickyDicky

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Ok Guys - heres some Verilog that ISE is spitting back at me with the following errors:

ERROR:HDLCompiler:255 - "X.v" Line 211: Cannot assign to memory pixel1_pipe directly
ERROR:HDLCompiler:698 - "X.v" Line 211: Part-select of memory pixel1_pipe is not allowed
ERROR:HDLCompiler:1373 - "X.v" Line 211: Unpacked value/target cannot be used in assignment


Code Verilog - [expand]
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reg [`DataN:0] pixel1_pipe [3:0];
 
always @ (posedge clk)
begin
    if (clken) begin
    
    //THis is what I want to do, but it falls over with an error
    //pixel1_pipe <= {pixel1_pipe[2:0], pixel1};
    
    //This is what I have to do.
    pixel2_pipe[0] <= pixel2;
    pixel2_pipe[1] <= pixel2_pipe[0];
    pixel2_pipe[2] <= pixel2_pipe[1];
    pixel2_pipe[3] <= pixel2_pipe[2];
    
    end
end


All it should be is a simple shift register, and it doesnt get angry with the VHDL equivalent. Is this just a Verilog syntax version thing?

Another questions - in version of verilog can a "reg" type be assigned with an "assign". It seems to throw its dummy out again assigning a reg with an input.

eg.
reg a;

assign a = 1;
 

Your commented out line is what you would use if pixel1_pipe were standard vector, but you made it a two dimensional array. IIRC the concatenation operator can not be used with arrays.

Assign is only used for wires.

SystemVerilog does away with the concept of reg and wire.

r.b.
 

rberek said:
Your commented out line is what you would use if pixel1_pipe were standard vector, but you made it a two dimensional array. IIRC the concatenation operator can not be used with arrays.
Click to expand...

I should have added that it simulates in modelsim fine - I am guessing its an SV vs Verilog thing.
 

I remember there being some quirks regarding multidimensional arrays in Verilog but it has been a while since I implemented one in Verilog. There are some people on here who ar far more versed in the minutiae of the language than I am so perhaps they could comment.

r.b.
 

If you want to make it look like a shift register in the coding:

Code Verilog - [expand]
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reg [7:0] pixel_pipe [3:0];
 
  always @ (posedge clk) begin
    {pixel_pipe[3],pixel_pipe[2],pixel_pipe[1],pixel_pipe[0]} <= {pixel_pipe[2],pixel_pipe[1],pixel_pipe[0],pixel};
  end


This is how I've done it in the past. I verified this does synthesize in xst.
 

rberek said:
SystemVerilog does away with the concept of reg and wire.
Click to expand...
I wouldn't go quite that far. Yes SystemVerilog makes it easier to assign to either a wire or reg in most cases, but you still can only use a wire where you need strength information to resolve multiple drivers.
 

Thanks! Good to know. To be honest I have never used anything other than "logic" in SV RTL.

r.b.
 

logic replaces reg in SystemVerilog and those two are equivalent. reg originally stood for register but that could be a misleading description.

If all the signals in your design have only one driver (i.e. no bidirectional signals) and you don't care about strength, the you don't need to use anything other than logic in SystemVerilog.
 

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