cross-clock domain FIFO question

Dear all,

I am having severe problem capturing data from the FIFO.
I want to inquire the possible cases when we have read and write clock both supplied from different sources and also having different frequency
Note that input width is 16, while output width is 64-bit since input is from ADC and output is to the computer

1. What possible problems can happens when the write clock is faster than read clock.
2. When read clock is faster than write clock.

I will be waiting for reply.

Bests,

forget about read clock/write clock questions - think in terms of data rates and FIFO depth.
If data rate write > data read then you will have a problem.
so in your case, assuming you write and read a value on every clock cycle, you need clocks so that read_clk >= write_clk/4.

if you have a slower speed on the read side, lets say write_clk/8, then you can only write for 1/2 the clock cycles. The FIFO depth then gives you the maximum burst size.

Thank you for reply.

I have ADC clock which is user selectable(i.e. user can select it ).
Minimum speed till now I have select is 50MHz and maximum speed is 250MHz...
But usual ADC frequency is 50MHz which is the write clock of ADC. and about the read clock, it is related to PCIe frequency. cmd_clk signal below is the rd_clk signal
I will quote you the manufacturer of the board.

Our reference designs only support a PCIe clock of 100MHz without spread spectrum. Then, cmd_clk is 125MHz (having a 100MHz PCIe clock), I will not be able to tell you how this clock is generated but it comes from the Xilinx PCIe core we use in our design.

Click to expand...

Please if possible can you share your experience about both the cases, i.e. read and write clock cycles are greater than each other...


Bests,

If the rates are mismatched you need to monitor both the full and empty flags from the FIFO to know if you can still write data (NOT-full) and keep reading (NOT-empty). If you don't do this then you'll end up loosing data or reading garbage.

In the full case you'll want to have some indication that this even occurred as it means you've potentially lost data as the writes are controlled by an ADC which I assume just spits data out at 50-250MHz.

For the empty case you may want to buffer up the data to whatever makes sense to send as a burst over PCIe.

you need a dual clock fifo. if you google it you wil find lots of staffs.

Actually the problem that I want to share is this( I have also shared it in other post and barry and ads_ee) have replied me very positive responses...
But I first try to recheck the previous things and improving the design again and I have now the following signals.(please check the images below).

The little description is as below...Note that trigger is the starting point of capturing signal(signal is not shown here in figure, hence trigger should be at time t=0 alwaaaays)
Now I (ONLY) THINK that this has something to do with fifo reading and/or writing unsynchronization, but am not sure and hence want an expert opinion...
or what possible causes can be...?

Signal capturing starts by an external trigger.(triggering frequency is 250Hz, i.e. after every 4ms new series of data should arrive from ADC).
For 1 single data all is well... but when I try to take multiple data with multiple triggers(FIFO size number of data at each trigger), I get data somewhat shifted (data lagging). The way I do it is after 1 trigger I read FIFO using DMA read and store in binary file in PC.(for 250Hz triggering frequency reading DMA and writing binary file should not pose problem...Should it...).
By the way when I slow down the triggering frequency to 50Hz, this shifting occurs after about 500 signals...

Write clock frequency = 50MHz, write width -> 16bit
read clock frequncy = 125Mhz (generated by PCIe IP prvovided by xilinx)
read width => 64 bits.

Please see the following figures where I have only shown the triggers (not the signal which start aftrer this trigger).
First figure is the first signal :
second figure is second signal, but isntead it captures 2 triggers
after this all the signals start at similar time as shown in figure 3.

Click to expand...

Bests and Thanks in advance

I suspect something happens between the 2nd and 3rd trigger that results in a FIFO overflow condition, which obviously never recovers. Have you run enough times to determine if there is a periodicity in the slippage?

This is why I suggested trying a ping-pong buffer with the read and write pointers always starting at address 0 so the data is always aligned with the t=0 position. Can't have slippage in that type of design.

You still haven't indicated if you've added any diagnostics to the design to determine if you're getting overflow/underflow in your FIFOs. That is the first thing I would do. Just run the signals to a spare pin and use a scope with persistence and see if you get any over/under flowing.

If you have Chipscope/SignalTap I would connect ILAs to the FIFO write and FIFO read logic, FIFO flags, data DMA requests from the PCIe core and use a synchronized (to both clock domains) version of the t=0 trigger as a capture trigger.

I get the feeling you haven't had a lot of experience debugging designs in hardware, it's a skill you should strive to develop. I'm assuming you have a TB for the design and it worked fine there? If so try modifying the stimulus to more closely match the hw if you can (I suspect there is a mismatch between the TB stimulus and the actual PCIe transactions).

- - - Updated - - -

BTW did you used the core generator to build a dual clock asynchronous FIFO? You didn't use a single clock FIFO by mistake? Also if you did add/use the FIFO flags like empty/full....empty should only be used by the read clock domain and full should only be used on the write clock domain. If you use them on the wrong domain you might see issues with data slippage. You really need to add over/under flow detection and send it to pins that you can monitor.

Not trying to be condescending, just want to make sure you correctly understand as I just checked your profile and found out your still a student
overflow would be done by looking for writes when the FIFO is full, in the write clock domain.
underflow would be done by looking for reads when the FIFO is empty, in the read clock domain.

what is the exact problem? Dual clock domain? or unwanted pulses?

Unwanted, timing of pulses is the exact problem...I am trying to figure it out.
dual clock domain is the necessity.

@ ads_ee...:smile:
well yes I am not very good at hardware level NOW... But I will surely ....:smile:
I don't have chipscope and I am using 3rd party development kit which communicates through PCIe,
so I will have to make registers inside FPGA and later monitor the value of register.

I will finish implementing the solutions today.

I think you cant handle a dual clock design. Your main problem is moving edges in different clock domains.