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That is vast field and is difficult to summarize all here. In brief,
In DRC, all drawing rule related to size and separations are checked. These rules are defined in design rule manual (DRM) of the process you are using. off grid violation also comes under DRC checks.
In LVS, we check the connectivity of layout with respect to schemtic. It has nothing to do with circuit functionality, meaning clean LVS doesn't mean your post layout simulation results will match with those with prelayout. That comes after implementing layout with following certain guidelines such as matching, limited parasitics etc.
Assura of cadence and Calibre of mentor are widely used for these checks.
Note: You could post this Q in analog layout forum of edaboard. This section is for digital design.
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