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    set_input_delay example

    Hi, guys,
    I am useing primetime, in my project there is a analog submodule and one digital submodule , i can use the ilm timing module to run primetime , my question is that can i use the set_input_delay and set_output delay same as the ports in the top level? the inputs and outputs are pins to the top level!!!

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    set_input_delay

    Hi, friends:
    why no anybody answer my question? pls help me , thank you all!!!!

    Maybe my expression not clear.

    here i add some points:
    when i use set_input_delay/set_output_delay in the internal pin,
    and report the timing from/to the pin, it's seems right, but i not sure , because
    i haven't see anyone do it like this before.



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    set_input_delay synopsys

    hello. Does PT support analog design? or you just view your analog sub_module as
    a black-box and just set some input and output constraints for it?



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    synopsys set_input_delay

    Quote Originally Posted by quake
    hello. Does PT support analog design? or you just view your analog sub_module as
    a black-box and just set some input and output constraints for it?
    Yes, the analog submodule or digital submodule to the top level is a blackbox,
    and i set input and output delay in the interface pins between them.



    •   Alt23rd November 2004, 10:28

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    set_input_delay set_output_delay

    I am wondering why you use PT to do the job, you are right, and PT is right too.
    but the result may not seem that meaningful, why not turn to spice for more accurate delay caculation?



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    set_output_delay -min

    Hi

    First of all, i don't think PT supports analog design.
    coming to the set_input_delay and set_output_delay part if the inputs and outputs in the top level are from the digital submodule, you can assign delay values depending on your time budget. but for ports coming from or going to analog sub module (or macro) you need not set input and output delays. istead, use set_false_path to eliminate them from timing analysis. also u can block the entire analog module from timing analysis. incase if signals are going from analog to digital sub module (as inputs) synchronise them to the digital module's clock and use them. also use set_false_path on these signals and the synchronisers.
    i hope this helps.

    ramakrishna



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    synopsys set_output_delay

    Quote Originally Posted by quake
    I am wondering why you use PT to do the job, you are right, and PT is right too.
    but the result may not seem that meaningful, why not turn to spice for more accurate delay caculation?
    Can you tell me why the result semms not meaningful?
    And the project is too large, as well as the frequency is higher also, so run spice
    will spend too long time , but if PT support this , this will help me.



    •   Alt24th November 2004, 01:43

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  8. #8
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    set_output_delay

    Quote Originally Posted by ramakrishna
    Hi

    First of all, i don't think PT supports analog design.
    coming to the set_input_delay and set_output_delay part if the inputs and outputs in the top level are from the digital submodule, you can assign delay values depending on your time budget. but for ports coming from or going to analog sub module (or macro) you need not set input and output delays. istead, use set_false_path to eliminate them from timing analysis. also u can block the entire analog module from timing analysis. incase if signals are going from analog to digital sub module (as inputs) synchronise them to the digital module's clock and use them. also use set_false_path on these signals and the synchronisers.
    i hope this helps.

    ramakrishna
    I think you are right in normal situation, here I emphasize analog submodule to top level is a black-box, and i don't think PT supports analog design too, but between analog submodule to my digital module there are some datapath, and i must care it , i think i can't set_false_path on these signals and use synchronisers,
    so if PT can analysis the datapath timing when i set input delay and output delay on them, it's good news to me.
    In facts, i have do like that, the report from PT seems OK, but i need an exactly
    answer.



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    how to black box the submodule in dc

    Since your analog block is treated as a black box, and it's interface timing is represented by ILM model, I think you can use set_input_delay/set_output_delay on top-level ports as usual.



    •   Alt24th November 2004, 06:48

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    set_false_path signals

    Quote Originally Posted by carrie
    Since your analog block is treated as a black box, and it's interface timing is represented by ILM model, I think you can use set_input_delay/set_output_delay on top-level ports as usual.
    hi, my question is that can i use the set_input_delay and set_output delay same as the ports in the top level? not using ilm timing module , it's too trouble to generate the timing module !

    But if PT can do it solely by setting set input delay and set output delay , this will
    simplfy the STA flow.



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    black box budgeting in prime time

    have you already verified those timing issues of your analog module? If you did, just translate the info to the PT with the delay when you realy hope to regard it as
    a black-box in the whole digital design. If not, the inferface of the mix_signal should be simulated. My advice is that since your design is large and fast, the timing issue should be taken very good care, if you think HSpice is slow try HSIM,
    maybe it will work by my estimate. Hope this can be helpful



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    primetime set_output_delay

    Hi, the dc, pt, pc, astro all support set input_delay and output_delay in submodule's ports.
    in this time, you dont read behavial model,but read
    link library.
    for input of the macro, you need set output_delay in top level, for output of the macro, you need set input_delay in top level. all are ok.



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    set_input_delay -min

    Quote Originally Posted by haosg
    Hi, the dc, pt, pc, astro all support set input_delay and output_delay in submodule's ports.
    in this time, you dont read behavial model,but read
    link library.
    for input of the macro, you need set output_delay in top level, for output of the macro, you need set input_delay in top level. all are ok.
    Hi , thanks.
    For example . the analog submodule have one output data path with :
    clk, data[15:0] , then i create a clock at the clk port of analog module , set
    input delay in data[15:0] related to clk, it's ok?



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    input port clock primetime

    yes. it is ok.
    but better way is create_generated_clock in analog module's clock input port,
    thus when do top-level clock tree synthesis, the port will be balanced with other related DFF's.
    you can get completely constraitn and better timing .



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    primetime internal pin

    Quote Originally Posted by haosg
    yes. it is ok.
    but better way is create_generated_clock in analog module's clock input port,
    thus when do top-level clock tree synthesis, the port will be balanced with other related DFF's.
    you can get completely constraitn and better timing .
    the clock port from analog submodule is a clock source , there is no phase
    relationship to the other clocks, so to my way of thinking i can't create generated clock on this port, do you think so?
    BTW, about use set_input/output_delay on port of submodule ,
    i can't find the related descriptions in sold, even one simple example , can you tell me why you confirm it? Thanks.



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    set_input_delay on all inputs other than clocks

    i think pt can't support analog design, you can use a psudo model for your analog part



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    set_output_delay synthesis constraints

    the clock port from analog submodule is a clock source , there is no phase
    relationship to the other clocks, so to my way of thinking i can't create generated clock on this port, do you think so?
    BTW, about use set_input/output_delay on port of submodule ,
    i can't find the related descriptions in sold, even one simple example , can you tell me why you confirm it? Thanks.[/quote]


    Hi, yes, this time you should create clock on the port.
    Synopsys solvnet is more effective than sold.
    And after setting timing constraint, you need run "chech timing" and "report_timing". You should verify the constraint by viewing detailed timing report. thus you can check if the constraint is your wanted, though in this time the timing report is not accurate.
    Don't rely on documents, the timing report will show you how does the tool understand constraint. you need make you are consistent with tools. i.e. make tools work accord with your instruments.
    Either DC and PT can do timing check, the PT more detailed.



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    primetime clock port

    Quote Originally Posted by haosg
    the clock port from analog submodule is a clock source , there is no phase
    relationship to the other clocks, so to my way of thinking i can't create generated clock on this port, do you think so?
    BTW, about use set_input/output_delay on port of submodule ,
    i can't find the related descriptions in sold, even one simple example , can you tell me why you confirm it? Thanks.

    Hi, yes, this time you should create clock on the port.
    Synopsys solvnet is more effective than sold.
    And after setting timing constraint, you need run "chech timing" and "report_timing". You should verify the constraint by viewing detailed timing report. thus you can check if the constraint is your wanted, though in this time the timing report is not accurate.
    Don't rely on documents, the timing report will show you how does the tool understand constraint. you need make you are consistent with tools. i.e. make tools work accord with your instruments.
    Either DC and PT can do timing check, the PT more detailed.[/quote]

    OK, I see.
    Thank you!



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    synopsys design constraint set_input_delay

    Hi,
    It 's OK.
    You can use set_in/output_delay for in/output of ANALOG BLACK-BOX. I just tapeouted a chip like this, a LVDS analog core is in the chip.



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