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DRC and LVS rules for TSMC 130nm libraries

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thanhFF

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Dear all,

I am working on an analog IC design project using TSMC 130nm technology. I have all the schematic, layout, simulation models but missing LVS, DRC rules for layout verification (assuraDRC.rul, extract.rul, compare.rul). Does anyone have these files? Can you please share with me if possible? I need these quite urgent and contacted MOSIS but they cannot process until after New Year :(

Thanks,
 

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