Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

"clock skew"-"clock delay"......PLL-DLL

Status
Not open for further replies.
S

SAV

Junior Member level 1
Joined
Aug 21, 2004
Messages
15
Helped
2
Reputation
4
Reaction score
0
Trophy points
1,281
Location
Colombia
Activity points
138
What's the diference beetwen clock skew and clock delay? and i want to know what's the diference beetwen a PLL and a DLL?.
 

Re: "clock skew"-"clock delay"......PLL-

Skew is the maximum of the clock delay difference between any two piont into the device where the clock is routed (FF clk input)
 

Re: "clock skew"-"clock delay"......PLL-

More precise clock skew is the clock delay between two consecutives devices or FF’s.
 

Clock skew is defined as the maximam clock delay between the clock inputs of filipflops in the same design for same clock.

Clock delay is the genra term used to represent the time it takes the device takes to give output when it presented with input w. r.t. clock domain.
 

Clock skew is the maximam difference of the delay time from the clock source to all the clock port of the flip-flops in that clock domain. And Clock delay, in this sense, is the average(mean) of the above delays.
PLL is for phase lock loop. In the sense of clock synthesizer, it contains a VCO(valtage control Oscilliator), generating output clock with a frequency M/N of the input reference clock, and the feedback loop that ensures the M/N relationship and the stability.
DLL is for Delay lock loop, instead of VCO, it contains only Delay array, that can only adjust the delay(phase), from the input reference clock, and sometimes, capable of generating 2X clock(Xilinx DCM).
 
  • Like
Reactions: ivlsi

    ivlsi

    ivlsi

    Points: 2
    Helpful Answer Positive Rating
Re: "clock skew"-"clock delay"......PLL-

I think that

1- Clock Skew: always measure the delay between two nodes drived from the same clock source and ideally the clock edge should arrive at the same time on both.

2- Clock delay: mainly defined for a transmission line ( or trace) so it may defined as x ns/ y mm. it also can be define the delay between two nodes (clock skew) by knowing the c/c's of the track connecting these nodes.

3- PLL: the conventiona analog Phase Locked Loop.
4-DLL: Delay or Digital locked Loop the digital implementation of PLL.
 
  • Like
Reactions: malden

    M

    malden

    Points: 2
    Helpful Answer Positive Rating
Re: "clock skew"-"clock delay"......PLL-

the skew generally mean clock path delay difference of two dff that are close.
but for clock tree the skew means maximus delay difference of clock path between all dff's that the clock drives.
clock delay means latency that delay from clock source to dff's CK pin.
PLL is phase-lock-loop, it is generally a analog.
DPLL is all-digital pll
DLL is delay-lock-loop. it also can be analog or all-digital.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top