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Question about low power implementation using cadence virtuoso

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VirtuosoDracula

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Hi All,

I'm trying to implement Muli-Supply Voltage technique to a design.

Basically, in my design I've two analog blocks operating at two different voltages, and I've attached a level shifter b/w the two. I've specified voltage of primary power net as 1.5 V for the first block and 1.8 for the second.So, now when I extract power intent from virtuoso, it creates a mode with nominal condition at 1v and maps all the domains to that condition.

So, in the nutshell I's like to know that is there any reason for the mapping to nominal condition when I've already specified voltages to the power nets?

Thanks in Advance.
VD!
 

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