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VHDL code problem design 8bit wide 2-to-1 multiplexer

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rara801

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ello guys...

i'm having a problem with the vhdl coding...
this my coding for 8bit wide 2-to-1 multiplexer....i need to connect the switches to red light LEDR and the the output to green light LEDG in de2 board but the problem the interface object "SW" of mode out cannot be read. Change object mode to buffer. how to solve this problem

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity part2_2 is
PORT( x:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      y:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     S:IN STD_LOGIC;
 SW:OUT STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
LEDG :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end part2_2;
 
architecture Behavior of part2_2 is
 
BEGIN
PROCESS(S)
begin
    if S ='0' then
        
        LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
        LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
        LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
        LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
        LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
        LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
        LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
        LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));
    ELSIF SW(17) ='1' then
 
        LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
        LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
        LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
        LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
        LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
        LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
        LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
        LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));
 
    end if;
    
 
SW(17)<=S;
 
LEDR(0) <= x(0);
LEDR(1) <= x(1);
LEDR(2) <= x(2);
LEDR(3) <= x(3);
LEDR(4) <= x(4);
LEDR(5) <= x(5);
LEDR(6) <= x(6);
LEDR(7) <= x(7);
 
LEDR(8) <= y(0);
LEDR(9) <= y(1);
LEDR(10) <= y(2);
LEDR(11) <= y(3);
LEDR(12) <= y(4);
LEDR(13) <= y(5);
LEDR(14) <= y(6);
LEDR(15) <= y(7);
 
 
LEDR(0) <= SW(0);
LEDR(1) <= SW(1);
LEDR(2) <= SW(2);
LEDR(3) <= SW(3);
LEDR(4) <= SW(4);
LEDR(5) <= SW(5);
LEDR(6) <= SW(6);
LEDR(7) <= SW(7);
 
LEDR(8) <= SW(8);
LEDR(9) <= SW(9);
LEDR(10) <= SW(10);
LEDR(11) <= SW(11);
LEDR(12) <= SW(12);
LEDR(13) <= SW(13);
LEDR(14) <= SW(14);
LEDR(15) <= SW(15);
LEDR(17) <= SW(17);
 
 
end PROCESS;
 
end Behavior;
 
Last edited by a moderator:

rara801 said:
ello guys...

i'm having a problem with the vhdl coding...
this my coding for 8bit wide 2-to-1 multiplexer....i need to connect the switches to red light LEDR and the the output to green light LEDG in de2 board but the problem the interface object "SW" of mode out cannot be read. Change object mode to buffer. how to solve this problem
Click to expand...

You answered your own question...change SW to 'buffer' rather than 'out'.

I'll also add a few other comments:
- You're not doing much driving of 'SW'. Only 'SW(17)' is being driven, the others bits are not driven. On the surface it appears that 'SW' should be an input, not an output (or buffer)...but maybe you just neglected to provide the code for driving SW.
- Your 'if S ='0' ...' statement for driving the bits of LEDG will cause latches to be created. You don't want that. The latch comes about because LEDG will not be assigned (and therefore will have to retain it's current state) if S /= '0' and SW(17) /= '1' (i.e. both 'if' are false).
- Your sensitivity list is incomplete. The process depends on more than just 'S', it also depends on 'x', 'y' and 'SW'. Your implemented hardware will not work the same way as the simulation.

Kevin Jennings
 

but how to crete the buffer command?? i'm still don't get it

Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
 
entity part2_2 is
PORT( x:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
      y:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
     S:IN STD_LOGIC;
  SW:BUFFER STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
LEDG :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end part2_2;
 
architecture Behavior of part2_2 is
 
BEGIN
PROCESS(S)
begin
    if S ='0' then
        
        LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
        LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
        LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
        LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
        LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
        LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
        LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
        LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));
    ELSIF S ='1' then
 
        LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
        LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
        LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
        LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
        LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
        LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
        LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
        LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));
 
    end if;
    
 
 
LEDR(0) <= x(0);
LEDR(1) <= x(1);
LEDR(2) <= x(2);
LEDR(3) <= x(3);
LEDR(4) <= x(4);
LEDR(5) <= x(5);
LEDR(6) <= x(6);
LEDR(7) <= x(7);
 
LEDR(8) <= y(0);
LEDR(9) <= y(1);
LEDR(10) <= y(2);
LEDR(11) <= y(3);
LEDR(12) <= y(4);
LEDR(13) <= y(5);
LEDR(14) <= y(6);
LEDR(15) <= y(7);
 
 
LEDR(0) <= SW(0);
LEDR(1) <= SW(1);
LEDR(2) <= SW(2);
LEDR(3) <= SW(3);
LEDR(4) <= SW(4);
LEDR(5) <= SW(5);
LEDR(6) <= SW(6);
LEDR(7) <= SW(7);
 
LEDR(8) <= SW(8);
LEDR(9) <= SW(9);
LEDR(10) <= SW(10);
LEDR(11) <= SW(11);
LEDR(12) <= SW(12);
LEDR(13) <= SW(13);
LEDR(14) <= SW(14);
LEDR(15) <= SW(15);
LEDR(17) <= SW(17);
 
 
end PROCESS;
 
end Behavior;


but i'm still got the other error..
 
Last edited by a moderator:

rara801 said:
but how to crete the buffer command?? i'm still don't get it
Code: 
library ieee;
use ieee.std_logic_1164.all;

entity part2_2 is
PORT( x:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	  y:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	 S:IN STD_LOGIC;
  SW:BUFFER STD_LOGIC_VECTOR(17 DOWNTO 0);
LEDR :OUT STD_LOGIC_VECTOR (17 DOWNTO 0);
LEDG :OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
end part2_2;

architecture Behavior of part2_2 is

BEGIN
PROCESS(S)
begin
	if S ='0' then
		
		LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
		LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
		LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
		LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
		LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
		LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
		LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
		LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));
	ELSIF S ='1' then --<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

		LEDG(7) <= (NOT (S) AND x(7)) OR (S AND y(7));
		LEDG(6) <= (NOT (S) AND x(6)) OR (S AND y(6));
		LEDG(5) <= (NOT (S) AND x(5)) OR (S AND y(5));
		LEDG(4) <= (NOT (S) AND x(4)) OR (S AND y(4));
		LEDG(3) <= (NOT (S) AND x(3)) OR (S AND y(3));
		LEDG(2) <= (NOT (S) AND x(2)) OR (S AND y(2));
		LEDG(1) <= (NOT (S) AND x(1)) OR (S AND y(1));
		LEDG(0) <= (NOT (S) AND x(0)) OR (S AND y(0));

	end if;
	


LEDR(0) <= x(0);
LEDR(1) <= x(1);
LEDR(2) <= x(2);
LEDR(3) <= x(3);
LEDR(4) <= x(4);
LEDR(5) <= x(5);
LEDR(6) <= x(6);
LEDR(7) <= x(7);

LEDR(8) <= y(0);
LEDR(9) <= y(1);
LEDR(10) <= y(2);
LEDR(11) <= y(3);
LEDR(12) <= y(4);
LEDR(13) <= y(5);
LEDR(14) <= y(6);
LEDR(15) <= y(7);


LEDR(0) <= SW(0);
LEDR(1) <= SW(1);
LEDR(2) <= SW(2);
LEDR(3) <= SW(3);
LEDR(4) <= SW(4);
LEDR(5) <= SW(5);
LEDR(6) <= SW(6);
LEDR(7) <= SW(7);

LEDR(8) <= SW(8);
LEDR(9) <= SW(9);
LEDR(10) <= SW(10);
LEDR(11) <= SW(11);
LEDR(12) <= SW(12);
LEDR(13) <= SW(13);
LEDR(14) <= SW(14);
LEDR(15) <= SW(15);
LEDR(17) <= SW(17);


end PROCESS;

end Behavior;

but i'm still got the other
Click to expand...





as you used SW() x() and y() to assign their values so you wipl have to add x y n SW in sensetivity list of process..
 
Last edited by a moderator:

jimmy_tag said:
vhdl is case sensitive change ELSIF to elsif.. It will work..
Click to expand...

100%, absolutely, positively WRONG!!!! VHDL IS NOT CASE SENSITIVE!!!!

But you're missing a lot of stuff from your sensitivity list. Everything on the right side of your assignment statements should be there.
 

barry said:
100%, absolutely, positively WRONG!!!! VHDL IS NOT CASE SENSITIVE!!!!

But you're missing a lot of stuff from your sensitivity list. Everything on the right side of your assignment statements should be there.
Click to expand...

Corrected myself.. Thanks..
 

jimmy_tag said:
rara801 said:
but how to crete the buffer command?? i'm still don't get it
Click to expand...

There is no 'buffer command'. A signal on an entity can be of the following modes:

in = Input only, cannot be assigned to
out = Output only, cannot be used as an input
buffer = Output, but the output value that is assigned can also be read and used inside the entity
inout = Input/Output. When used as an input the signal is being driven by some external device or entity. Generally is of no use in FPGA/CPLD designs except at the top level of a design when interfacing to some physical device (like RAM) that happens to have a bi-directional bus. FPGA/CPLDs typically do not have any internal signals that can be driven by more than one source so the synthesis tool will typically flag an error when trying to build such a device.

You don't say what your 'other error' is all about so nobody can really help here. Simply posting your code and not copy/pasting the error message isn't very helpful.

Kevin Jennings
Click to expand...
 

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