High frequency interface issue

Hello everybody!

Considering a typical FR4 substrate, the characteristic impedance Z0 of a microstrip transmission line grows as the line width decreases. It is thus mecanically more complicated to work at a much higher impedance level than 50Ω. No doubt with this.

But assuming you can connect a high impedance antenna (e.g. 3-wires folded dipole -> Z0 =~ 500Ω-2000Ω) to an integrated circuit using 2 minimal length bondwires. The input impedance of the IC is about 10Ω-j*100Ω @ 2.5 GHz (RC series model). It is known that the loaded Q of the system increases with the real impedance level. What else limits you in the choice of the impedance level of the antenna? And what about the interface issues at high impedance levels?

Thanks for your opinion!

Hi,
You normally avoid high impedances (this is avery relative term) at high frequencies. As the signal may find an alternate path of lower impedance very easily reulting in significant loss.
B R M

Yes, but how could i calculate an upper limit for these losses considering the substrate losses and the impedance level?

Thks[/quote]