Thread: What are the different approaches for counter design?

hi

Can any one of you tell what are the different approaches for counter design. I do not want the types of counter like mod2,mod4...... . I want what r the ways in which this counter can be done. If possible give me a good link.

Hi,
You may use a state Machine approach for counter design. You define what are the next states and then genrate the circuit based on the type of flip flop you want to use?

B R
Madhukar

Ref: An engineering approach to digital design -- William Fletcher

Basic component of counter is gate. If you want to know detailed structure, you can refer to microelectrical related books, there are detailed information.

actually, how many approaches are there to design a divide by n counter?

Originally Posted by Edward_2288

actually, how many approaches are there to design a divide by n counter?

Depends how do you want to look at it. There are many ways. I am putting a figure using 7490 decade counter IC.

There are two basic ways to divide by N. The digital logic methods described above use storage elements such as latches and feedback paths to make a state machine. They have the property of holding the value when the clock is removed.

There is another way that is all analog. The signal to be divided is applied to a mixer. The output is the desired frequency. A part is split off and multiplied by N-1 which is put into the other mixer input. This idea goes back over 60 years. It produces the lowest phase noise of any division method. It costs a high amount (money and power consumption and volume/weight) though.

Originally Posted by flatulent

There is another way that is all analog. The signal to be divided is applied to a mixer. The output is the desired frequency. A part is split off and multiplied by N-1 which is put into the other mixer input. This idea goes back over 60 years. It produces the lowest phase noise of any division method. It costs a high amount (money and power consumption and volume/weight) though.

And is far more complex then buying counter ic's. right?

flatulent the second method, is fancy and complex, is employed what I think is of fully developed commercial entities and of course army reseach projects maybe (they have plenty of money) using this method.
I believe he wants it for school lab work/project.

flatulent thank you for the second method. I learned something new today.

Correct. The all analog way is much more expensive than buying a counter IC. However it is the only way if you want the lowest possible phase noise in your system or if the system operates above 10 GHz or so where the low cost counters such as from Hittite IC company stop working.

Here's a diagram the clever analog frequency divider (R. L. Miller 1939) that flatulent is describing. It's not a counter.

Image shamelessly snitched from this paper: http://icd.el.utwente.nl/publication...php?pub_id=173

counter design can be done by using a state machine approach if u r designing a synchronous counter.for ripple counter u can refer to digital logic design by
holdsworth and woods.

could i ask a question....

if we write the VHDL code for state machine or any other digital system design....how do v c the synthesize circuits....or how do v get the picture of the logic gates design....

i m using max+plus II.....i cannot find any option to c the synthesize output by the vhdl code.....


thanxs in advance.....

how do we simulate/measure the phase noise contribted by the divider?

How the Values of N ( Counter value) affects the Phase noise.

Pls reply

Thanks & regards
SavithRu

The best way would be to go with flip flops... first write down the sequence that you have to count... then find out the transition in each outputs at each stage...
for the flip flop that you gonna use find out the combinational input based on their transistion tables... all text books deal with such approach only...

How're you going to implement it? Using discrete components or will implement it in an IC ?

Steps for designing a counter(for synchronous conunter)

write down the sequence , couter must follow..
Select the flip flop u want to use..
Write the flip flop exitation table and using K map, find how to connect the output of one FP to another.....

Take care that , the counter is not entered to undefined states....

Any sequential circuit can be designed by state machine approach..
For a counter, after the state machine flow, it can be designed using any one of the four types of flipflops(D ff, T ff, JK ff, RS ff)