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flash FPGA vs CMOS FPGA

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mahmoudathab

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I have been using spartan 3E for a while now but I am considering switching to actel IGLOO flash FPGA series. is there any difference between the 2 FPGAs (programming-wise )?. will I need additional equipment or not?
 

Besides the obvious tool chain differences, a different JTAG pod, different device architecture. You can still use Verilog/VHDL to write your RTL description, but you'll have to keep in mind the difference in architecture.
 

Having a FLASH fabric - Actel is inherently non-volatile while SRAM based FPGAs (Altera/Xilinx/Lattice) must load from every power-up from an external flash.
Both are programmed using a JTAG interface.

FLASH based FPGA's are much less power hungry. They also seem to have the benefit of requiring less power supplies (of different voltage level), so PCB integration should be easier.

They are however much smaller devices (logic wise) - Xilinx and Alera offer greater densities.
Also, I think the ACTEL design tools are much worse.

What's wrong with your spartan 3E ?
 
shaiko said:
Having a FLASH fabric - Actel is inherently non-volatile while SRAM based FPGAs (Altera/Xilinx/Lattice) must load from every power-up from an external flash.
Both are programmed using a JTAG interface.

FLASH based FPGA's are much less power hungry. They also seem to have the benefit of requiring less power supplies (of different voltage level), so PCB integration should be easier.

They are however much smaller devices (logic wise) - Xilinx and Alera offer greater densities.
Also, I think the ACTEL design tools are much worse.

What's wrong with your spartan 3E ?
Click to expand...

Nothing is wrong with the spartan but I am in a highly "power sensitive" project so obviously the spartan 3E was out of the question :)
Also what do you mean that the ACTEL design tools are "much worse" ? Should I be expecting problems along the way?
 

Also what do you mean that the ACTEL design tools are "much worse" ? Should I be expecting problems along the way?
Click to expand...

They use "Synopsys - Synplify" for synthesis wich is rather OK. But the place & route tool is made by Actel.
Compared to ISE it feels "low quality". More crashes, bugs , less intuitive and less user friendly.
With that said - I have to note that in the end it does work and will produce a functioning design. I've used Actel IGLOO nano and PROASIC 3 in high reliability projects.
 
shaiko said:
They use "Synopsys - Synplify" for synthesis wich is rather OK. But the place & route tool is made by Actel.
Compared to ISE it feels "low quality". More crashes, bugs , less intuitive and less user friendly.
With that said - I have to note that in the end it does work and will produce a functioning design. I've used Actel IGLOO nano and PROASIC 3 in high reliability projects.
Click to expand...
I could work with that :) thanks man I appreciate it. do you mind if I contact you within the next few weeks if I needed more information?
 

They use "Synopsys - Synplify" for synthesis wich is rather OK. But the place & route tool is made by Actel.
Compared to ISE it feels "low quality". More crashes, bugs , less intuitive and less user friendly.
With that said - I have to note that in the end it does work and will produce a functioning design. I've used Actel IGLOO nano and PROASIC 3 in high reliability projects.
Click to expand...
The current version of Libero uses Synplify Pro, which does have some nice features of register balancing and schematic generation similar to ISE. I've noticed over the years that Synplify has lost ground to both Altera and Xilinx synthesis in terms of QoR. The Libero back end tools definitely feels low quality as in antiquated compared to the latest versions of ISE. Libero is more akin to Xilinx's Foundation series of tools back in the late 90s.

You should keep aware you will likely need to select a much larger part (based on number of logic elements) than what you would normally use for a Spartan 3E design as the building blocks (basic logic elements) in the Actel parts is unlike the Xilinx/Altera LUT/Register combination cell. You can easily eat up a large number of versatiles in the Actel architecture that would require only a small number of CLBs in a Xilinx part. For example we have a SPI slave which takes approximately 200 LUTs in a Virtex 6 part which after cutting out over half the programmable registers in the design took up 90%+ of a ProAsic3 nano 20K part. (YMMV)

Regards,
-alan
 
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do you mind if I contact you within the next few weeks if I needed more information?
Click to expand...
I'll be glad to help.
 

ads_ee said:
The current version of Libero uses Synplify Pro, which does have some nice features of register balancing and schematic generation similar to ISE. I've noticed over the years that Synplify has lost ground to both Altera and Xilinx synthesis in terms of QoR. The Libero back end tools definitely feels low quality as in antiquated compared to the latest versions of ISE. Libero is more akin to Xilinx's Foundation series of tools back in the late 90s.

You should keep aware you will likely need to select a much larger part (based on number of logic elements) than what you would normally use for a Spartan 3E design as the building blocks (basic logic elements) in the Actel parts is unlike the Xilinx/Altera LUT/Register combination cell. You can easily eat up a large number of versatiles in the Actel architecture that would require only a small number of CLBs in a Xilinx part. For example we have a SPI slave which takes approximately 200 LUTs in a Virtex 6 part which after cutting out over half the programmable registers in the design took up 90%+ of a ProAsic3 nano 20K part. (YMMV)

Regards,
-alan
Click to expand...

Alan are you sure about this? because if you are that would mean to expect some problems along the way.
 

It may help if you describe the main elements in your design and estimated required I/Os.
 

shaiko said:
It may help if you describe the main elements in your design and estimated required I/Os.
Click to expand...

alright this is the project: I am trying to implement an insulin pump using ACTEL IGLOO FPGA and these are the components I would like to implement inside the FPGA:
1. ADC using successive approximation register.
2. A memory card (the size is still unknown but it has to be large enough to store data from a continuous glucose sensor and other events such as basals and boluses for at least 7 days).
3. real time clock
4. LCD interface
5. keypad interface
6. a multiplexer
7. a USB connection
8. not to mention the software to operate the pump and to interface to the glucose sensor.

this image might help
pump.jpg

oh and the I/Os are approximately 40
can all this be implemented using ACTEL AGL125 chip (which has 125,000 logic gates) or should I look for something bigger?

and I am trying to use this kit: http://www.actel.com/products/hardware/devkits_boards/igloo_icicle.aspx
 

Why did you decide to use an FPGA ?
It seems like your project will be easier (and cheaper) to implement with a uC.
An ARM Cortex M3 like a hand for a glove...
 
mahmoudathab said:
Alan are you sure about this? because if you are that would mean to expect some problems along the way.
Click to expand...

The results of that port were definitely surprising based on Actel's counting of "gates". Though after looking at Actel's logic element it's not surprising. There's not much logic in them to begin with.

I agree with shaiko you should probably consider a micro.

Hmmm, the block diagram shows a micro. ;-)
 
Last edited:
well the idea is to try to build the system on a chip. and the FPGA presented a challenge :)

- - - Updated - - -

Untitled23.jpg
ok a simple question. I implemented an old stop watch project with Libro. did this project took up to 7%??

- - - Updated - - -

shaiko said:
Why did you decide to use an FPGA ?
It seems like your project will be easier (and cheaper) to implement with a uC.
An ARM Cortex M3 like a hand for a glove...
Click to expand...

Shaiko there must be hundereds of MCUs out there. Why did you propose the ARM cortex M3? Any special features?
 

When it says 7% - I think it means that the design stretches over that portion of the device. That doesn't necessarily mean that it can't take less space! The tool made no such effort, because it didn't have to.
To elaborate - think of the back row of a regular passenger car. I've seen once a group of 5 people cramp in that confined space. However, if you seat there by yourself and assume the most comfortable position with your legs stretched - you may well occupy more than a single seat!
Same thing with your ACTEL - the tool sees that your design is small and all alone. Therefore it makes no effort farther compacting it...

About the MCU option:
ARM is the most popular and scalable plattform to date.
Its tool support and vedors availability is simply incomparable to any other.
Also, upgrading in the future will be much easier.
By itself the Cortex M3 is a very capable device:
It's 32 bits, has hardware divide and multiple, low power and usually comes with a vast array of peripherials (the last has more to do with the vendor's implementation than with the actual ARM core).
The M3 has established itself as THE industry standard in the microcontroller market.

Simply put:
If I needed VERY low power consumption (the lowest possible) with low processing capabilities - I'd go with a Microchip PIC or TI MSP430.
If I needed VERY high processing capabilities at resonably low power I'd go for a TI or FREESCALE DSP.
From your description I conclude that your project falls under neigther of the above requirements. You need a microcontroller with analog capabilities, capable peripherals and all that at low power - Cortex M3 will fit that bill perfectly.

I suggest you look under the following vendors for the most suitable Cortex M3 for your application:

1. Cypress
2. ST
3. FREESCALE

Good luck
 
shaiko said:
When it says 7% - I think it means that the design stretches over that portion of the device. That doesn't necessarily mean that it can't take less space! The tool made no such effort, because it didn't have to.
To elaborate - think of the back row of a regular passenger car. I've seen once a group of 5 people cramp in that confined space. However, if you seat there by yourself and assume the most comfortable position with your legs stretched - you may well occupy more than a single seat!
Same thing with your ACTEL - the tool sees that your design is small and all alone. Therefore it makes no effort farther compacting it...

About the MCU option:
ARM is the most popular and scalable plattform to date.
Its tool support and vedors availability is simply incomparable to any other.
Also, upgrading in the future will be much easier.
By itself the Cortex M3 is a very capable device:
It's 32 bits, has hardware divide and multiple, low power and usually comes with a vast array of peripherials (the last has more to do with the vendor's implementation than with the actual ARM core).
The M3 has established itself as THE industry standard in the microcontroller market.

Simply put:
If I needed VERY low power consumption (the lowest possible) with low processing capabilities - I'd go with a Microchip PIC or TI MSP430.
If I needed VERY high processing capabilities at resonably low power I'd go for a TI or FREESCALE DSP.
From your description I conclude that your project falls under neigther of the above requirements. You need a microcontroller with analog capabilities, capable peripherals and all that at low power - Cortex M3 will fit that bill perfectly.

I suggest you look under the following vendors for the most suitable Cortex M3 for your application:

1. Cypress
2. ST
3. FREESCALE

Good luck
Click to expand...

thank you shaiko for all the information :D

- - - Updated - - -

ads_ee said:
The results of that port were definitely surprising based on Actel's counting of "gates". Though after looking at Actel's logic element it's not surprising. There's not much logic in them to begin with.

I agree with shaiko you should probably consider a micro.

Hmmm, the block diagram shows a micro. ;-)
Click to expand...

thanks Alan :D
 
Last edited:


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