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sdc constraints for a path starting and ending in a same flop

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vimalraj205

vimalraj205

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hai friends

i have a setup violation in a path starting in the Q pin of a flipflop followed by some logic blocks and ending in the D pin of the same flip flop

how can i over come this

can i set false path or multicycle path


help me...........


thank you
 

vimalraj205 said:
hai friends

i have a setup violation in a path starting in the Q pin of a flipflop followed by some logic blocks and ending in the D pin of the same flip flop

how can i over come this

can i set false path or multicycle path


help me...........


thank you
Click to expand...

Setting false path or multicycle is dependent upon your logic design. If you designed it to be multicycle then you can set that and fix your problem. If you designed it to be a false path then I would question why you would even have a path.

Your other hope is with clock skew. Clock skew will reduce your setup time to account for the fact that the clocks on your sending and receiving flops may be skewed. That cannot happen in this case so make sure that you are not subtracting the skew.
 

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