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[SOLVED] pac simulation on sample and hold circuit

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Hi all,
during the simulation of the sample and hold circuit, i have encountered one problem. the circuit is a simple sample and hold circuit consisting of a switch and a capacitor. the input is vsin with pac mag set to 1. after simulation, when the sampled voltage at the capacitor becomes 0.5 instead of 1.
when i ran trans simulation, the sampled voltage matches with the input sine wave.
anyone has any idea why the sample voltage becomes half during the pac simulation?

thanks very much for your help
 

thanks for your reply.
2012-11-22_155915.jpg
the circuit is attached. c1/c2=5.
when i ran trans simulation, the gain is 5. but during pac simulation, the gain is only 2.
 

i found that in the pac simulation if the input is discrete signal, the gain is 5, while if the input is continuous, the gain is 2..
anyone can help to explain why this happens? thanks very much.
 

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