zhaniko93
Newbie level 1
Consider a simple CPU .
Here, REGFILE write is sequential, so it has to accomodate Setup and Hold time requirements: data on WD and WE(write enable) has to be valid TSetup time before valid clock transition, but only after clock transition, propagation delays of Instruction memory, Control logic and some other things, become WD and WE valid. that is, not TSetup before clock transition, but even propagation times after clock transition become they valid, which violates setup and hold time constraints, so it shouldn't work, but it works! it is MIT 6.004 lab N6 and that one works, why? P.S. I think I opened thread in a slightly wrong place. sorry, but couldn't find more appropriate place
Here, REGFILE write is sequential, so it has to accomodate Setup and Hold time requirements: data on WD and WE(write enable) has to be valid TSetup time before valid clock transition, but only after clock transition, propagation delays of Instruction memory, Control logic and some other things, become WD and WE valid. that is, not TSetup before clock transition, but even propagation times after clock transition become they valid, which violates setup and hold time constraints, so it shouldn't work, but it works! it is MIT 6.004 lab N6 and that one works, why? P.S. I think I opened thread in a slightly wrong place. sorry, but couldn't find more appropriate place