Pipeline operation in Examples

Hi all,

Here is a 5-stages pipeline:
InstructionFetch->InstructionDecode->Execute->MemoryAccess->WriteBack

Could someone explain what happen in each stage for following processor commands:
1) a = a +1
2) a = b + c
3) jump ADDR

Thank you!

Hi!

Well, actually the answer depends on the processor model you are assuming: in-order? out-of-order? This is important, since it points out aspetcs of hazards resolution and pipeline stalls.

Cheers

Just take the simplest example and provide your answer. I just wonder what happen in each pipeline stage for a given operation (let's say for arithmetic add of two values stored in different locations in the Memory).

Ok,

so assume we have a MIPS-like ISA, such as the one from MIPS R3001. In this, assuming registers are already available, an addition is computed using a single instruction as follows:
where R1 is the register where the result will be stored, and R2 and R3 are the source registers. Now, the execution of the instruction adherese to the following scheme (cycle-by-cycle):

CYCLE#1: instruction is fetched from memory, and information is copied to the IF/ID latch registers;
CYCLE#2: instruction is decoded, and contents of source registers are copied;
CYCLE#3: addition is executed, and the result of the operation will be forwarded to the next stage;
CYCLE#4: since the ADD is an arithmetic instruction, nothing particular is done in the MEM stage;
CYCLE#5: the result of the execution (stored temporarily in the MEM/WB latches and forwarded from the EXE/MEM latches) is written to the register identified by the TAG (R1)

Now, in your case what is different from this scheme is that the addition is done through an immediate (a constant), so only one source register is required; then, the compiler is smart enough to generate the following machine code for your instruction 1):
in which the content of variable a is loaded into register R1, which will be used in the following immediate addition. With this in mind, there should be no reason to stall the pipeline. The other instructions will be managed in the same way and interleaved accordingly. For the unconditional jump, the PC will be updated depending to the label of the JUMP instruction.

Notice that, however, the compiler will delete the first of your instructions, and leave only instructions 2) and 3) since there are two consecutive writes to the same variable (WAW).

Cheers