Milestone
Newbie level 3
Hello,
I need to design a 8:1 serializer circuit with 25MHz word clock and 200MHz bit clock, with google, I found that I need one load signal which have a duty cycle of 1/8. Can any one tell me how to generate this load signal?
I found one paper here:
https://hsi.web.cern.ch/hsi/s-link/devices/golproto/PaperLEB99.pdf
in Figure 4.
It generate the load signal with DFFs. It seems it regenerate the word clock with the bit clock.
I have several questions regarding this design.
Is it possible to generate the load signal just with DFFs?
Is it possible not to regenerate the word clock(no clock shift with input word clock)?
and is it possilbe to generate the load pulse at the falling edge of the word clock(I want to sample the data when it is stable)?
Or can anybody tell me which book or paper i can refer to?
Thanks very much!
Milestone
I need to design a 8:1 serializer circuit with 25MHz word clock and 200MHz bit clock, with google, I found that I need one load signal which have a duty cycle of 1/8. Can any one tell me how to generate this load signal?
I found one paper here:
https://hsi.web.cern.ch/hsi/s-link/devices/golproto/PaperLEB99.pdf
in Figure 4.
It generate the load signal with DFFs. It seems it regenerate the word clock with the bit clock.
I have several questions regarding this design.
Is it possible to generate the load signal just with DFFs?
Is it possible not to regenerate the word clock(no clock shift with input word clock)?
and is it possilbe to generate the load pulse at the falling edge of the word clock(I want to sample the data when it is stable)?
Or can anybody tell me which book or paper i can refer to?
Thanks very much!
Milestone
