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input delay in testbench

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naught

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I want to in the real system, is the input already ready and stable before the 1st clk rising edge?
I mean, if there`s a reset signal, after the reset signal de-assert, the first clk comes, 1st clk. Is the input ready before the 1st signal, or ready at the exact time when the clk rises, thus causing 1 clk delay?

I`m puzzled here, because this would cause my logic to work different. plz tell me how the real input be prepared...
thx in advance...
 

It will all depend on how the reset works. Is it synchronous with the clock? Is the input asynchronous? You havent provided information.
 

TrickyDicky said:
It will all depend on how the reset works. Is it synchronous with the clock? Is the input asynchronous? You havent provided information.
Click to expand...

the reset, or enable signal is asynchronous. If the reset deassert/ enable assert before the clk rise, how is the data_in prepared? As far as i see, if the data_in change at the same time when clk rises, then the first input is wasted... I want to know how to handle this... thx in advance.
 

if you have a fully async reset, then yes you could have problems as data may violate setup and hold times for the first clock. Often the answer is the make the reset synchronous to the clock. So for an async reset - synchronise it. As long as it is synchronised, it should be ok to then connect to the async reset of the registers.
 

TrickyDicky said:
if you have a fully async reset, then yes you could have problems as data may violate setup and hold times for the first clock. Often the answer is the make the reset synchronous to the clock. So for an async reset - synchronise it. As long as it is synchronised, it should be ok to then connect to the async reset of the registers.
Click to expand...

thx a lot, TrickyDicky ^0^.
so is it dominant that in real systems, the designer tend to use synchronous reset signal? People around me always use the async reset...so in most cases can it be called a bad design?
 

naught said:
People around me always use the async reset...so in most cases can it be called a bad design?
Click to expand...

not exactly, as Tricky said - synchronize the reset and use it as async. input to registers;
the advantage of such approach is that the async. reset is an independent input to FPGA cell so
doesn't consume data inputs;

j.a
 

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