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Need some help with the small-signal circuit model

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wandola

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Hey,

Can anybody help me or explain to me how to develop the small-signal model of the circuit.

The NMOS in one of the branches of the input stage is biased by some voltage. I think it will affect the 1st stage gain. Can anyone help me with this?

The second stage is kinda of crazy. Usually the signal from the 1st stage going to gate. But this circuit, it is not the case. I don't know how to draw the SS circuit of the 2nd stage as well..


Thanks a lot guys.
 

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The second stage is class AB push-pull output buffer. If output of first stage (amplifier stage) is going up, M7 is turning off and M8 is turning on
 

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