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[How-it-works] SDF Back Annotation

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ivlsi

ivlsi

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Hi All,

How does the SDF Back Annotation work? Should it be used along with WLM? How does the tool extract the required info (transition and other delays)?

Do the SDF files include routing (length/cap/resistance/etc) as well as placement (cell's coordinates) information?

Thank you!
 

SDF back annotation works in relation with Verilog model.
SDF should included the net delay or more detailed the path delay, and the cells delay.
 

"SDF back annotation works in relation with Verilog model" - are you talking about a Verilog model, which is defined in technology libraries (*.lib)?
 

no verilog model used for post-layout simulation, you should see a description related to timing, which three default values , and the simulator could applied the new value provided by the SDF.
 

three default values
Click to expand...
Min, max and typical delays?

SDF back annotation works in relation with Verilog model
Click to expand...
Where is the Verilog model located? you wrote it's not in the *.lib file... so, where? Which file does also include functional behavior of the cell?

Thank you!

- - - Updated - - -

As for capacitance, resistance and length of the nets, should they also be derived from P&R tool? is there any usage of these values in the Post-Layout Logic Synthesis?

As for SDF file(s), are they usually generated for several corners? How many SDF files should I receive from Layout group? Which one of them should I use for Post-Layout Logic Synthesis?
 

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