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VHDL code for a Finite State Machine

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lahrach

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Hi all,

How can I encode a state machine such that when I click a button it run all possible states.

regards
 

For example: consider this FSM

FSM={state_1, state_2, state_3, state_4, state_5,
state_6, state_7}

signal start : std_logic;

when statr<='1'

state_1 ->state_2 ->state_3 ->state_4 ->state_5 ->state_6 ->state_7 ->state_1

regards
 

sounds like you're on to solving your problem - keep goinng
 

thank you for this answer
 

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