plz anyone correct this coding

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module fulladder(a, b, c_in, sum, c_out);
input a;
input b;
input c_in;
output sum;
output c_out;
wire x,y,z;
xor (x,a,b);
xor(sum,x,c_in);
and(y,a,b);
and (z,x,c_in);
or (c_out,z,y);
endmodule
 
 
module fourbitadder(a, b, c_in, sum, c1);
input [1:0] a;
input [1:0] b;
input c_in;
output [1:0] sum;
output c1;
wire c0;
fulladder fa0(a[0],b[0],c_in,sum[0],c0);
fulladder fa1(a[1],b[1],c0,sum[1],c1);
endmodule
 
 
 
// another    2 bit ripple carry adder
module fourbitadder1(a, b, c_in, sum, c3);
input [3:2] a;
input [3:2] b;
input c_in;
output [3:2] sum;
output c3;
wire c2;
assign c_in=0;
fulladder fa0(a[2],b[2],c_in,sum[2],c2);
fulladder fa1(a[3],b[3],c2,sum[3],c3);
endmodule
 
module BCD2Excess1 (X, B);
output [2:0] X; //declare output ports
input [2:0]B; //declare input ports
wire [2:0] X;
 //watch the changes of inputs
 //form the output signals in
//terms of input signals
assign X[0] = ~B[0];
assign X[1] = (B[0] & B[1]) ;
assign X[2]= (B[2] ^ (B[0] & B[1])) ;
endmodule
 
//
// 6:3 MUX
//
module mux(X,bin,out);
input X;
input bin;
output out;
wire [2:3]sum;
wire c3;
assign bin[0]=sum[2];
assign bin[1]=sum[3];
assign bin[2]=c3;
wire [2:0] X;   // input a
wire [2:0] bin;   // input b
wire [2:0] out; // output (obviously)
wire       c1; // selection thingy
assign out = c1 ? X : bin;
endmodule
 
module csa(A,B,cin,sumout,cout);
input [3:0]A;
input [3:0]B;
input cin;
output [3:0]sumout;
output cout;
wire [3:0]a;
wire [3:0]b;
wire c_in;
wire c_out;
wire [2:0]X;
wire [2:0]B;
wire bin;
wire out;
 
fulladder m1(a, b, c_in, sum, c_out);
fourbitadder m2(a, b, c_in, sum, c1);
fourbitadder1 m3(a, b, c_in, sum, c3);
BCD2Excess1 m4(X, B);
mux m5(X,bin,out);
 
assign sumout[2]=out[0];
assign sumout[3]=out[1];
assign cout=out[2];
endmodule