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[STA] posedge / negedge & Multi-Cycle

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ivlsi

ivlsi

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Hi All,

Let's say we have two flops connected back-to-back. One of the flops works on posedge, another on the negedge of clock.

For the correct STA, should a multi-cycle path be defined between these flops?

Are there any HOLD requirements for the second flop? Could you imaging a scenario where it has no Setup violations, but do has Hold violations?

Thank you!
 

it is a half-cycle path and hold violation willl not happen but set up is highly possible.
 

Should a multi-cycle of 1/2 clock be defined for the second flop?
 

"have to keep ur logis's less"? - how is it affected by setting a multi-cycle constraint?
 

see you have a half-cycle path when u connect a pos-edged flop with neg-edged one. So the total time available is clk_cycle/2-setup. hence ur logic should be less than this time value. if a designer confirms it to be a multi-cycle path, then there can be a relaxation for the amount of logic that can be accommodted. so it all lies in the design.
 

hm... can I define a multi-cycle path as a ratio of a clock cycle (e.g. 0.5*T)?

If I don't define this path as a multi-cycle one, how STA tools deal with it?

Thank you!
 

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