CIC decimation filter: does bit pruning affect the gain?

// cic decimation filter : R=64, M=1, N=3
module cicdecim64 (x_in,y_out,clk,reset);
input			clk; 
input 			reset;
input signed	[11:0]	x_in;
output signed 	[11:0]	y_out;
reg signed 		[11:0] y;

parameter hold=0, sample=1;
reg			clk2,state; 	//sample or hold states
reg		[5:0]	count;			//count till 63 starting from 0
reg signed	[11:0]	x;					//input
wire signed	[27:0]	sx;				//sign extended input
reg signed	[27:0] 	i0;				//Integrator output section 0
reg signed	[22:0]	i1;				//output section 1 under the consideration of Haugenauer's pruning
reg signed	[17:0]	i2;
reg signed	[15:0] 	z0, c1, c0; 	// Integrator+COMB 0
reg signed	[14:0] 	z1, c2;
reg signed	[13:0] 	z2, c3;



always @(negedge clk)
begin : FSM 							// finite state machine
case (state)
hold : begin
if (count<63) 							// setting states for downsampling
state <= hold;
else
state <=sample;
end
default:
state <= hold;
endcase
end

assign sx={{16{x[11]}},x_in};

// Integrator
always @(posedge clk or reset)begin
if(reset) begin
count = 0;
x = 0;
i0 = 0;
i1 = 0;
i2 = 0;
c0 = 0;
c1 = 0;
c2 = 0;
c3 = 0;
z0 = 0;
z1 = 0;
z2 = 0;
y=0;
end

begin: I
x <= x_in;
i0 <= i0 + sx; 						
i1 <= i1+i0[27:5];
i2 <= i2+i1[22:5];
case (state) 								//downsample
sample : begin
c0 <= i2[17:2];
count <= 0; 								//reset counter once a sample has been fetched
end
default :
count <= count+1;
endcase
if((count>16)&&(count<32))
clk2 <=1;
else
clk2 <=0;
end
end


// COMB
always @(posedge clk2)
begin: COMB
z0 <= c0;
c1 <= c0-z0;
z1 <= c1[15:1];
c2 <= c1[15:1]-z1;
z2 <= c2[14:1];
c3 <= c2[14:1]-z2;
y	<=c3[13:2];
end
assign y_out=y; 
endmodule

-- --------------------------------------------------------
-- Program for the design of a CIC decimator.
-- --------------------------------------------------------
--      Input bit width      Bin  =    12
--      Output bit width     Bout =    12
--      Number of stages     S    =     3
--      Decimation factor    R    =    64
--      COMB delay           D    =     1
--      Frequency resolution DR   =    64
--      Passband freq. ratio P    =    10
-- --------------------------------------------------------
-- ----------------- Results of the Design ----------------
-- --------------------------------------------------------
-- -------- Computed bit width:
-- -------- Maximum bit growth over all stages      =    18 
-- -------- Maximum bit width including sign Bmax+1 =    30 
-- Stage   1 INTEGRATOR. Bit width :  28 
-- Stage   2 INTEGRATOR. Bit width :  23 
-- Stage   3 INTEGRATOR. Bit width :  18 
-- Stage   1 COMB.       Bit width :  16 
-- Stage   2 COMB.       Bit width :  15 
-- Stage   3 COMB.       Bit width :  14 
-- ------- Maximum aliasing component : 0.001307 = 57.68 dB
-- ------- Amplitude distortion       : 0.951694 =  0.43 dB