kannan2590
Member level 4
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity subfilt0 is
Port ( dout : out STD_LOGIC_vector(28 downto 0);
clk : in STD_LOGIC;
clk1:in std_logic;
reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0));
end subfilt0;
architecture Behavioral of subfilt0 is
component DFF is
port(
q : out STD_LOGIC_vector(27 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
d :in STD_LOGIC_vector(27 downto 0) -- Data input from the MCM block.
);
end component;
signal H00,H048 : STD_LOGIC_vector(19 downto 0) := (others => '0');
signal MCM00,MCM01 : STD_LOGIC_vector(27 downto 0) := (others => '0');
signal add_out01: STD_LOGIC_vector(28 downto 0) := (others => '0');
signal Q01 : STD_LOGIC_vector(27 downto 0) := (others => '0');
begin
H00 <= "11111111111111100101";
H048 <= "00000010101101101100";
dff1 : DFF port map(Q01,Clk,MCM00);
p01000rocess(Clk1,reset)
begin
if reset='0' then
dout <= "00000000000000000000000000000";
elsif clk1'event and clk1='1' then
MCM00 <= din * H00;
MCM01 <= din * H048;
add_out01 <= Q01+ MCM01;
dout <= add_out01;
end if;
end process p01000;
end Behavioral;
this is the code in vhdl for 2 coefficient fir filter.for distributed arithmetic form what changes i have to make .whether the above code is correct.This code may generate overflow problem.whether distributed arithmetic solve the problem of overflow .where can i get the the information about distributed arithmetic and vhdl libraries and packages . i tried to increase the output width so that carry over at the last bit can be considered but then also i did not get the desired result. is there any solution to the above problem.
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity subfilt0 is
Port ( dout : out STD_LOGIC_vector(28 downto 0);
clk : in STD_LOGIC;
clk1:in std_logic;
reset : in STD_LOGIC;
din : in STD_LOGIC_vector(7 downto 0));
end subfilt0;
architecture Behavioral of subfilt0 is
component DFF is
port(
q : out STD_LOGIC_vector(27 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
d :in STD_LOGIC_vector(27 downto 0) -- Data input from the MCM block.
);
end component;
signal H00,H048 : STD_LOGIC_vector(19 downto 0) := (others => '0');
signal MCM00,MCM01 : STD_LOGIC_vector(27 downto 0) := (others => '0');
signal add_out01: STD_LOGIC_vector(28 downto 0) := (others => '0');
signal Q01 : STD_LOGIC_vector(27 downto 0) := (others => '0');
begin
H00 <= "11111111111111100101";
H048 <= "00000010101101101100";
dff1 : DFF port map(Q01,Clk,MCM00);
p01000rocess(Clk1,reset)
begin
if reset='0' then
dout <= "00000000000000000000000000000";
elsif clk1'event and clk1='1' then
MCM00 <= din * H00;
MCM01 <= din * H048;
add_out01 <= Q01+ MCM01;
dout <= add_out01;
end if;
end process p01000;
end Behavioral;
this is the code in vhdl for 2 coefficient fir filter.for distributed arithmetic form what changes i have to make .whether the above code is correct.This code may generate overflow problem.whether distributed arithmetic solve the problem of overflow .where can i get the the information about distributed arithmetic and vhdl libraries and packages . i tried to increase the output width so that carry over at the last bit can be considered but then also i did not get the desired result. is there any solution to the above problem.