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How to find all combinatorial path from inputs to outputs ?

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xworld2008

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about synthesis

in a module, how to find all combinatorial path from inputs to outputs, i think that write a scripts can do it. i don't know how to write? somebody help me?
 

about synthesis

Use PT to report?
Maybe pt can find these paths.
 

about synthesis

i didnt understand your question..
u want to find out all combo paths from inputs to outputs??

You can read the code or use Debussy nSchema to analyze easily..

if u want to find combo delay from i\p to o\p
try
report_timing -from NAME -to NAME
 

Re: about synthesis

If you mean how synthesis tools do it, You should check any paths from inputs to outputs which do not pass through your clocked always block in Verilog (process block in VHDL).

Regards,
KH
 

Re: about synthesis

I means that in my design, there are some paths that are combinatorial paths from input port to output port, i need a script to find all these combinatorial paths.
I know that using "report_timing -from <input port> -to <output port> can report directly,but now in my design, there are hundreds of port, So i wan to write a scripts to identify these combinatorial paths.
who can help me?
 

Re: about synthesis

If you are using DC, there are no commands to find the combinatorial paths. Just read the HDL code, or use HDL analyser such as Debussy.
 

Re: about synthesis

set_max_delay -from [all_inputs] -to [all_outputs]
report_timing -from [all_imputs] -to [all_outputs] -max_paths 10000
 

about synthesis

dc can list all the path ,
the path cross boundary will be!
 

Re: about synthesis

seperate sythesis the module and user primtime to report all path.
 

Re: about synthesis

use report_timing -to end_point
then DC will list the path was passed through what combinational cell.
 

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