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Serial in Parallel out register

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n_sanjay_n

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Hi everyone,

I want to design a serial in parallel out shift register that can hold the value of its output as long as the load bit is high. For example, if I wanted to design a 3 bit SIPO, the input to that would be something like this:

Code:
Entity sipo is 
generic (n : integer :=1);
Port (psin, load: in std_logic;
      pclks,prsts: in std_logic;
      psout:inout std_logic_vector(n-1 downto 0));
end sipo;
where psin is the serial input. After 3 clock cycles of the load bit being high, i.e. after all registers get the desired values, if i then put the load bit to 0, the output should still remain at the previous value.

Thanks.

- - - Updated - - -

Hey guys,

I am so sorry but I could solve the problem myself. I have posted the code below:

Code:
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
Entity sipo is 
generic (n : integer :=1);
Port (psin, load: in std_logic;
      pclks,prsts: in std_logic;
      psout:inout std_logic_vector(n-1 downto 0));
end sipo;
architecture arch of sipo is 

component d_ff
port(
d, clk, reset : in STD_LOGIC;
q : out STD_LOGIC);
end component;

component and_gate is
port (a,b : in std_logic ;
c : out std_logic);
end component;

signal clk : std_logic;

begin
  
  and1: and_gate port map(a => load, b => pclks, c => clk);

  bit1:d_ff port map(
    d => psin,
    clk => clk,
    reset =>prsts,
    q => psout(n-1));

sipo_generate:
for i in (n-2) downto 0 generate

bit_i: d_ff port map(
     d => psout(i+1),
	 clk => clk,
	 reset => prsts,
	 q => psout(i));	 
	 end generate;
end  arch;

Thanks you.
 

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