---
+ Post New Thread
Results 1 to 7 of 7
  1. #1
    Newbie level 6
    Points: 159, Level: 2

    Join Date
    Oct 2012
    Posts
    14
    Helped
    0 / 0
    Points
    159
    Level
    2

    How to use 2 condition in assign [verilog]

    Hi, I have learnt how to use system verilog but this is my first time to use verilog. So I have a question about how to use 2 condition in assign.

    I have 3 input (a,b,c) and 1 output (z)
    For System verilog, I will do it like that:
    always_comb //always_comb is the same function as assign
    begin
    if(a==b)
    z=a;
    else
    if (b==c)
    z=b;
    end
    For verilog: //this is doing the first part of function, how can I put the second part into this assign?
    assign z = (a & b) ? a:z; //I know thats wrong since a=/=b , this will output z for z. What should I write if a=/=b, it will do " if (b==c)
    z=b;
    Thanks for the help
    Ivan
    Last edited by daisordan; 17th October 2012 at 16:15.

    •   Alt17th October 2012, 16:09

      advertising

        
       

  2. #2
    Advanced Member level 2
    Points: 3,833, Level: 14

    Join Date
    Dec 2011
    Location
    Fremont, CA, USA
    Posts
    538
    Helped
    230 / 230
    Points
    3,833
    Level
    14
    Blog Entries
    4

    Re: How to use 2 condition in assign [verilog]

    Your always_comb blocks is not combinatorial - if a != b, and b != c, then there is no assignment to z and you have a latch. Your second if statement needs an else clause.

    In any case, the conditional ?: operator can be nested:

    assign z = (a==b) ? a : (b==c) ? b : z;

    That z at the end represents the missing else clause.
    Dave Rich
    Verification Technologist
    Mentor Graphics Corporation


    1 members found this post helpful.

    •   Alt17th October 2012, 17:34

      advertising

        
       

  3. #3
    Full Member level 6
    Points: 1,708, Level: 9
    ads_ee's Avatar
    Join Date
    Oct 2012
    Location
    San Diego
    Posts
    328
    Helped
    88 / 88
    Points
    1,708
    Level
    9

    Re: How to use 2 condition in assign [verilog]

    Equivalent code to System Verilog:
    Code Verilog - [expand]
    1
    2
    3
    4
    
    always @ * begin
      if (a==b)       z = a;
      else if (b==c) z = b
    end

    This works in System Verilog too as it's a superset of the Verilog language
    Code Verilog - [expand]
    1
    
    assign z = a==b ? a : b==c ? b;

    Regards,
    -alan


    1 members found this post helpful.

    •   Alt17th October 2012, 17:35

      advertising

        
       

  4. #4
    Advanced Member level 5
    Points: 12,962, Level: 27
    mrflibble's Avatar
    Join Date
    Apr 2010
    Posts
    2,368
    Helped
    594 / 590
    Points
    12,962
    Level
    27

    Re: How to use 2 condition in assign [verilog]

    always_comb is the same function as assign
    Uhm, no? It's in the rough same area of things that look like similar stuff, but I would not say they are identical.

    Even easier ... if you want to do it in verilog, and are a bit miffed that plain old verilog doesn't have "always_comb" ... well you can always use "always". So in your case:

    Code Verilog - [expand]
    1
    2
    3
    4
    5
    6
    7
    8
    
    always @* //always, just like always_comb functionally speaking is somewhere in the same galaxy as assign. sometimes.
    begin
        if(a==b)
            z=a; 
        else 
            if (b==c) 
                z=b;
    end

    Incidentally, what is z supposed to be when a!=b and b!=c ? Your code snippet doesn't have much to say about that situation...

    - - - Updated - - -

    Heh, this seems like a popular minute for replies! XD

    Updated update: awwww, the "Updated" messed my minute. That makes me very sad. ;(


    1 members found this post helpful.

  5. #5
    Newbie level 6
    Points: 159, Level: 2

    Join Date
    Oct 2012
    Posts
    14
    Helped
    0 / 0
    Points
    159
    Level
    2

    Re: How to use 2 condition in assign [verilog]

    Thanks guys :)
    I understand how does the assign use now. Since my output z is a wire, so I used assign for my code.

    1 more question, how about if I wanna do two things after a==b? Like:

    if(a==b)
    begin
    z=a;
    count=count+1;
    end
    else
    if (b==c)
    begin
    z=b;
    count=count+2;
    end
    Then what should I write them into assign? This is what I have tried

    assign z = (a==b) ? (a & (count=count+1)) : (b==c) ?( b & (count=count+2)): z;
    mrflibble: Could you briefly talk about why always_comb and assign are different? because when I read some verilog beginner's book, it said that are doing the same things.



  6. #6
    Advanced Member level 2
    Points: 3,833, Level: 14

    Join Date
    Dec 2011
    Location
    Fremont, CA, USA
    Posts
    538
    Helped
    230 / 230
    Points
    3,833
    Level
    14
    Blog Entries
    4

    Re: How to use 2 condition in assign [verilog]

    daisordan,

    If you want your code to be synthesizable, you cannot combine combinatorial and sequential logic like this in a single assign statement. You will need to explain your desired functionality without using any Verilog syntax first so we can suggest the best way to code what you want to achieve.

    If you don't care if your code is synthesizable, you can assign the output of a function call

    Code:
    assign z = myfunction(a,b,c);
    function logic myfunction(input a,b,c);
      if(a==b)
         begin
         z=a;
         count=count+1; // this is a side-effect that is not synthesizable
         end
      else
        if (b==c)
           begin
           z=b;
           count=count+2; // this is a side-effect that is not synthesizable
          end
    endfunction
    The biggest difference between always_comb and an assign statement is with the how the simulator deals with the semantics of function calls. An assignment statement only looks for events on the operands that appear on the RHS of the assignment, while always_comb expands functions in-line and looks for any change of any operand that appears inside the function. For example suppose I re-wrote the function to directly reference a,b,c instead of passing them as arguments to the function:
    Code:
    assign z1 = myfunction();
    always_comb z2 = myfunction();
    function logic myfunction();
      if(a==b)
         z=a;
      else
        if (b==c)
           z=b;
       else z ='bx; // a don't care to prevent a latch
    endfunction
    The asssign z1= statement would never execute because there are no triggering events on the RHS to cause an evaluation.

    The always_comb z2= block executes at time 0, and when there is a change on any operand that is referenced within the block.

    mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like

    Code:
    real pi;
    `define PI 3.14159
    always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead
    that fails because there was never an event to trigger the always @(*) block.
    Dave Rich
    Verification Technologist
    Mentor Graphics Corporation



  7. #7
    Advanced Member level 5
    Points: 12,962, Level: 27
    mrflibble's Avatar
    Join Date
    Apr 2010
    Posts
    2,368
    Helped
    594 / 590
    Points
    12,962
    Level
    27

    Re: How to use 2 condition in assign [verilog]

    Quote Originally Posted by daisordan View Post
    mrflibble: Could you briefly talk about why always_comb and assign are different? because when I read some verilog beginner's book, it said that are doing the same things.
    See for example this here link for a list of fun differences. :)

    - - - Updated - - -

    Quote Originally Posted by dave_59 View Post
    mrfibble, I recommend NEVER TO USE always @(*) because it does not guarantee execution at time 0. I have Seen code like

    Code:
    real pi;
    `define PI 3.14159
    always @(*) pi = `PI; // DO NOT EVER DO use always_comb pi = `PI; instead
    that fails because there was never an event to trigger the always @(*) block.
    I readily agree with that recommendation. :) I was just going with the OP's flow of it being verilog-2001 as opposed to system verilog.

    No always_comb in the old school verilog, hence the always @(*) remark. But when you have the luxury of tools that do system verilog, then I'd say go for always_comb, always_ff etc.

    The pointer to make sure you know what happens at time 0 in your simulation is a good one to remind oneself of...



+ Post New Thread
Please login