Verilog Divider/Multiplier/Adder Integers Question

Hi, my code currently looks like this. Is there any way my code can accept non integer numbers (A=3.05). I read that my output has to be a reg type so how can we represent multiplication, division or addition using non integers?

For ex. 3.05 + 1.07 or 1.06*5.01. If the output must be of type reg.


I read online that there are very complicated algorithms to do this but is there anything simpler. This is my test code. I want to add multiplication and addition as well.

Any help will be appreciated!

Thank You


`timescale 1ns/1ps

module test(clk,A,B,Y);
input clk;
input signed [9:0] A;
input signed [6:0] B;
output signed [15:0] Y;
reg signed [15:0] Y;


always @(posedge clk) begin

Y <= A/ B;

end
endmodule


TEST BENCH

`include "test.v"
`timescale 1ns/1ps

module tb_test();

reg clk;
reg [9:0] A;
reg [9:0] B;
wire signed [15:0] Y;
initial begin
clk = 0;
A = 8;
B = 10;
#500 $finish;
end


always begin
#1.6 clk = ~clk;
end

test call(clk, A, B, Y);

endmodule

Thanks again

Google around for "verilog fixed point" and you'll find some inspiration...

Can you please be more specific? I looked up fixed point in google and didn't find any good source. Can you recommend a good source or help me with a basic fixed point adder? I tried to understand this https://amakersblog.blogspot.com/2008/07/fixed-point-arithmetic-with-verilog.html but as it said my simulator just gave me integers.