source to substrate MOS transistor connection

Hello,

I have couple of basic questions

1. To avoid the threshold voltage variation with source voltage we can connect the bulk to source, but can we practically connect them with every technology or just with SOI and why ??

2. if we connect the bulk to source and suppose if the source voltage is high, assume of NMOS ,then I can see there is a forward diode from the p substrate to the drain , how we the avoid this diode ?

may be in short you can tell me about the condition of shortening the bulk to substrate

thanks

senan said:

1. To avoid the threshold voltage variation with source voltage we can connect the bulk to source, but can we practically connect them with every technology or just with SOI and why ??

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In std. CMOS technologies you can do this just for pMOS, because you can give it its own pWELL. All nMOS have to be in the same p-substrate. Double or triple well CMOS processes and SOI offer this possibility also for nMOS transistors.

senan said:

2. if we connect the bulk to source and suppose if the source voltage is high, assume of NMOS ,then I can see there is a forward diode from the p substrate to the drain , how we the avoid this diode ?

Click to expand...

We can't avoid it, but it's a reverse diode: drain (n+) is more positive than substrate (p).

senan said:

in short you can tell me about the condition of shortening the bulk to substrate

Click to expand...

You probably think of shorting source to bulk. Only possible if the FET has its own isolated well or substrate (SOI).

Thank you erikl, your answer is perfect for me

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one more, it came to my mind. If we have at least one possibility to connect one transistor (bulk and source) either PMOS or NMOS in the general single well process then why dont connect it, why usually the designers connect both of them to the substrate ?

senan said:

If we have at least one possibility to connect one transistor (bulk and source) either PMOS or NMOS in the general single well process then why dont connect it, why usually the designers connect both of them to the substrate ?

Click to expand...

As I told you above, for NMOS in the classic single well process (nwell on p-substrate) this isn't possible, because all NMOS have to be in the p-substrate. In such process, only PMOS can have their own wells.

And why stacked PMOS do not always get their own wells (in order to be able to connect their source to bulk)?
1. because it's not always necessary and one can live well with its larger |Vth| (and may be other disadvantages)
2. because isolated wells need additional space (and larger spacing).

Hi Senan,
In NMOS, if it's conducting, source potential can't jump above that of drain's, even in the case of body effect elimination. Similar is true for PMOS.
Shortening bulk with source is preferred in PMOS as if done in NMOS, substrate isolation is area hungry process and eats up significant area in nwell processes.