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how to add a delay using a variable in system verilog

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gadagkar.rohit

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Hello,

I am new to system verilog. I am trying add a randomized delay to a module.

i tried doing this, but didnt work

del = $urandom_range(0, 9);

data_dev_slot <= ##del wr_data[index];


can somebody please help me on this.

Thanks,
Rohit
 

"didn't work" is not a very helpful description of your problem. What happened versus what did you expect to happen?
 

sorry for that

my timescale is 1ns/100ps

the delay that i am using is

int del = urandom_range(0, 9);

thereafter i am using

data_dev_slot <= #del wr_data[index];

i am running this in loop so that i get a different delay everytime. but i am getting a delay of 1200ps, 200ps, 2400ps. 600ps.

I am not getting why am i getting fractional values for delays.
 

How are you measuring these delays? What kind of loop that controls when your non-blocking assignment statement executes?
 

for each iteration the delay is fixed.
in each loop i am driving each bit of the wr_data.

initially the data was driven at posedge of clk, but now i am using this
@(posedge clk_sdcard_slot_in);
for (int i=data_width-1; i>=0;i--) begin
data_dev_slot <= #del wr_data[index];
data_dev_slot_en <= #del 1;
index++;
end

now i am measuring the delay from the posedge of the clk.


Thanks,
Rohit
 

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