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How to balance the skew if we have two clocks domains in a design

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kapil_vlsi1

kapil_vlsi1

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How to balance the skew if we have two clocks domains in a design.

Please help
 

Hi kapil we have to use sync logics in order to balance the skew.
I am attaching a image file.

Regards
kpsr clock domains.png
 

The tools usually have such capability. For example, Synopsys ICC has "clock_opt -inter_clock_balance".
 
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