Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

low voltage NOT gate below 0.7V

Status
Not open for further replies.
M

movingbait

Member level 2
Joined
Apr 23, 2004
Messages
48
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
444
good day.

does anyone know anything about low voltage analog logic , of particular to me is how a not gate is made (the building block for everything).

i dont think its possible with transistors/FET's as they have a minimum of 0.7V drop so ...

If anyone could provide further hints i would appreciate.

movingbait Ü
 

if you work in low voltage deep-submicron process, the threshold voltage is no longer as high as 0.7V. If you really need to work with supply voltage at the level of 0.7 V (may be 0.13um or even 0.09um process??), the Vth should be in the range of 0.3 - 0.5 or 0.6V, thus your logic gate still can be turned on. Technology scaling almost all for digital trends, so it MUST work with digital circuits (if not int*l will not give money to fab with 0.09 um).
 

    M

    movingbait

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top