compare the signal using verilog in modelsim

I would like to compare the signal using verilog. Lets say I have a counter that output a random number in random timing. The clock is 20ns. For example:

count = 1 (20ns)
count = 3 (40ns)
count = 5 (80ns)
count = 3 (100ns)

Then I will have a output z, which will become 1 when the count value is changed. In this example:

z = 1 (20ns)
z = 1 (40ns)
z = 1 (80ns)
z = 1 (100ns)

I have tried to store the count value and do the comparison therefore I need to use synchronous logic. But the z will output 1 clock cycle late since the synchronous. If I use combinational assign, it cannot store the value and do compare.

Anyone can give me some hints how can I solve this problem?

Thanks

You didn't explain why you think to need a signal z and how it's generated. Your example suggests that the count value is changing every clock cycle.

Thanks FvM,

z is the recovery signal. In my project, I have to inject some faults in the CPU and the fault will be recovery while the signal changes (signal count in the example).
My problem is how can I generate the signal z? The count value is not changing every clock cycle, sorry I didnt make it clear before:

count = 1 (20ns)
count = 3 (40ns)
count = 3 (60ns)
count = 5 (80ns)
count = 3 (100ns)

count may stay in the same value (40ns to 60ns) or it may changes to anther value (60ns to 80ns)

How about explaining your problem in terms of clock cycles, not ns. I have no idea what a recovery signal is or even if it matters.

Thanks dave and sorry for my poor explaination

The count is generated in the module, it output the count value in random time and random value.
1 clock -> count = 1
2 clock -> count = 3
3 clock -> count = 3
4 clock -> count = 5
5 clock -> count = 3

The recovery is the output depends on the count value changes, it will be 1 when count value changed:

1 clock -> recovery = 1
2 clock -> recovery = 1 // At clock 1 to 2, count value change from 1 to 3, therefore recovery = 1
3 clock -> recovery = 0 // At clock 2 to 3, count value doesnt change, it stay at 3, therefore recovery = 0
4 clock -> recovery = 1 // At clock 3 to 4, count value change from 3 to 5, therefore recovery = 1
5 clock -> recovery = 1

What I have done is the count value. But now I dunno how can I detect the changes of count value. I have tried to store count value in each cycle and do comparison using always @, and then the recovery output will delay 1 clock cycle. If I use assign, I am not able to store the count value and do compare.

I hope I make it clear now

I see another misunderstanding. You have clarified, that the code is intended for a testbench. There's no need to use synchronous logic for a testbench. You can also use all kinds of timed statements to scan a signal at arbitrary times. Nevertheless the problem can be solved in synchronous logic if you want to.

Thanks FvM
Sorry for my poor english, i guess my bad presentation make you confused. All of those things are done in the Program counter module, not testbench. Is there any hints for me to detect the changes of count value?

I don't see, why it won't be possible to detect a counter value change and store or compare the new value in the same clock cycle. Why don't you simply try to write behavioral code (under a posedge clock condition) that does just this?