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circuit for accurate delay cell in cmos technology ?

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cmos_ajay

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I need to make a delay cell in standard CMOS technology. Typical delay is 10 nano seconds.
Is there circuit that is accurate over process, voltage and temperature changes ? Can anyone mention names of technical documents for reading ?

- Thanks in advance.
 

It is a good paper. Do you have any architecture of the delay cell I need ?
 

Do you have a reference clock? If so then a current-starved
DLL of N stages such that N*10nS=period, and a replica cell
sharing the bias but signal-path-independent, is a good
approach.
 

If you just want to delay a logic signal, have you tried sizing an inverter chain? Delay chains are widely used for self-timed operation in high-speed systems. You have to numerically optimize the widths to make it less sensitive to process variation and temperature.
 

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