Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Different delay in Behavioral and Timing Simulation

Status
Not open for further replies.

fmaximovic

Junior Member level 2
Joined
Aug 14, 2012
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,439
Hi all,

suppose that I have a block whose task is adding 1 to its input and output the result after 1 clock delay; also suppose that the behavioral simulation worked just fine.

If the post-PAR (timing simulation) shows a different result, i.e. that the result comes out after 2 clock delays (see the attached figure), what could be the problem?

bitmap.png

Thanks guys
 

something in the code. Please post the code.
 

something in the code. Please post the code.

Sure. Actually the block performs a sum between two inputs. Here are its ports

Code:
clk: in std_logic;
	 reset: in std_logic;
	 en: in std_logic; -- enable
	 A1 : in  std_logic_vector(7 downto 0);
         A2 : in  std_logic_vector(7 downto 0);
         SUM12   : out std_logic_vector(8 downto 0)


while this is the main process

Code:
aws_p : process (clk,reset)
   variable aws_tmp : std_logic_vector(8 downto 0);
   begin
		if reset='1' then
			SUM12<=(others=>'0');
		elsif (CLK'event*and*CLK='1') then
			if en='1' then 
				aws_tmp := conv_std_logic_vector(conv_integer(A1) + conv_integer(A2),9);
				SUM12 <= aws_tmp;
			end if;
		end if;
   end process;

In the testbench, the inputs vary synchronously with the clock. Also, my constraint file contains only a period specification.
 

you might want to check the rtl diagram - see if ISE is treating aws_tmp as a signal rather than variable. Or just remove the variable assignment altogether.
 

The simulation in post #1 is missing one input signal. Also the exact timing relation of clock and input matters. It can't be seen from the waveform, we need to see the textbench code. It would be much clearer if you change the input data not exactly at the clock edge.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top