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IR2110 and mosfet IRFPE50PB for sine-inverter

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sabu31

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Hi

I am designing a 250w sine pwm inverter(H-Bridge). The dc link voltage will be 400V volts. And output required is 230Vrms.

I am driving the inverter using IR2110 and the switches used are IRFPE50PBF. The pwm frequency is 50kHz. However on runnning the devices gets heated within a minute. I tried simple square pwm with 50% duty ratio ,50Khz. This time no heating was observed. I wanted to know what could be the cause of heating, whether its due to conduction loss (Rdson=1.2 ohm) or whether its due to anti parallel diode(trr=980ns). I put a dead band of 1micro second.How do i reduce the heating.Is reducing the switching frquency the only method to reduce the heating .
, are there better devcies rated for 50kHz, and 1kW operation.

thanking you.
 

sabu31 said:
Hi

I am designing a 250w sine pwm inverter(H-Bridge). The dc link voltage will be 400V volts. And output required is 230Vrms.

I am driving the inverter using IR2110 and the switches used are IRFPE50PBF. The pwm frequency is 50kHz. However on runnning the devices gets heated within a minute. I tried simple square pwm with 50% duty ratio ,50Khz. This time no heating was observed. I wanted to know what could be the cause of heating, whether its due to conduction loss (Rdson=1.2 ohm) or whether its due to anti parallel diode(trr=980ns). I put a dead band of 1micro second.How do i reduce the heating.Is reducing the switching frquency the only method to reduce the heating .
, are there better devcies rated for 50kHz, and 1kW operation.

thanking you.
Click to expand...

Dear,
For HF SPWM generation 20Khz is sufficient.. try reducing the switching frequency and then report back the outcomes...and to further reduce switching loses you can go with unipolar SPWM..in these type of SPWM one side high/low switches at HF SPWM pattern in complementary fashion..and the other side low/high switches at just 50 HZ frequency .. this all results in only one LC filter filter ..with just one Inductor and one Capacitor...which further helps in improving overall efficiency....

Added Later : Why are you using those mosfets..there are many other low Rdson/high voltage types of mosfets available.
 
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Hi
Thanks for the reply. When i reduced switching frequency to 20khz, the heating has reduced. However I am still confused as when i give square pwm of 50% duty at 50Khz there was no heating observed, but when i give sine pwm there is heating. So is the heating due to switching loss or conduction loss.. Is there any relation of reverse recovery time of body diode of mosfet to heating.. Thanking you.
 

It's due to switching loss. When switching frequency increases, switching loss increases as well. And remember that, as frequency increases, current required to turn the MOSFET fully on increases, as the gate must be charged in a smaller time. So, maybe, the problem lies in MOSFET gate drive section. What is the value of the gate current-limiting resistor? What voltage are you using to drive the MOSFETs?
 
Tahmid said:
It's due to switching loss. When switching frequency increases, switching loss increases as well. And remember that, as frequency increases, current required to turn the MOSFET fully on increases, as the gate must be charged in a smaller time. So, maybe, the problem lies in MOSFET gate drive section. What is the value of the gate current-limiting resistor? What voltage are you using to drive the MOSFETs?
Click to expand...

Hi Tahmid

Thanks for the reply. The value of gate resistor is 10ohms and gate driver Vcc is 15V. However as I mentioned before, for the same switching frequency of 50Khz, if we give square pwm of 50% duty ratio,there is no heating. But when the PWM is ,lets say 90% for upper switch and 5% for lower and another 5% for dead band, there is heating. Why is this so..?
 

Hi

I havent got answers for heating of switch at 50khz, at extreme duty cycles as compared to 50% duty cycle. Can i get some references regarding the solution to this problem..

Thanking you.
 

Dear,
there can be many reasons for that.. but to start first you need to capture several screen shots of waveforms at mosfet drains and at mosfet gates and paste here in forum...that will make things more clear..

and yes one more thing..did you tried PWM frequency @ 20 Khz/duty cycle 90+%..and then observed heating ? was it all ok? or same thing happened as what was happening @ 50Khz PWM frequency?
 

sabu31 said:
Hi

I havent got answers for heating of switch at 50khz, at extreme duty cycles as compared to 50% duty cycle. Can i get some references regarding the solution to this problem..

Thanking you.
Click to expand...

One possibility is that, at higher duty cycles, the MOSFET is not being fully turned on. You may need to use a larger bootstrap capacitor. What is the value of the bootstrap capacitor you are using now?
 

Yes, at higher duty cycles more gate charge is required from driver than at 50%, and also it increases with the switching frequency. 20khz is good enough, if you want to be at 50khz then improve your driver circuit, as tahmid said, you need to have a larger bootstrap capacitor, kindly share some observed waveforms so the exact situation may be more clear.
 

at higher duty cycles more gate charge is required from driver than at 50%, and also it increases with the switching frequency
Click to expand...
First point, no, second point, yes. Tahmid is referring to incomplete bootstrap capacitor charge which is a different problem.
 
Look this schematic....I think that you have problems because you dont have delay circuit. When you turn on high side and switching off low side without dalay you have short circuit between supply and ground for very small time, but that is enogh for heating. In this schematic D1,C1 and R1 make hardware dalay. You can also make software delay.
 

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I think that you have problems because you dont have delay circuit.
Click to expand...
Did you notice that the original post reports a dead time of 1 us? That's already quite a lot for MOSFETs.

I try to understand what's the test setup said as "50% duty cycle". Do I understand right that it involves zero load current while the sine PWM case is with load current? Than it's no fair competition.

Regarding the discussed problem of minimum low duty cycle to maintain bootstrap operation.
- <95% duty cycle should be usuallly sufficient
- if the capacitors are large enough and the sine output frequency isn't too low, you can even go for 100 % peak duty cycle
 
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Hi all

Thanks for the comments..

The Bootstrap capacitor is 4.7uF(electrolytic)+.33(ceramic).
The sine frequency is 50Hz

I am attaching the wave forms(gate-source and drain-source) at different duty ratios(50% with dead band,upto 90%with dead band) In actual operation duty ratio goes up to 95%.



The top two waveforms are for the upper switch .The glitches in the circuit are perhaps because the dc link to the inverter is supplied by a dc-dc boost converter. The glitches does not affect the sine waveform output.

Also I wanted to know whether the body diode reverse recovery time cause any difference in this circuit.

The heating is reduced at 20k switching as compared to 50k, however at 90% duty cycle at 20k there is more heating as compared to 50% duty at 20k.
 

Ýou didn't comment my guess that load current is the true difference between the cases responsible for low respectively high losses. The waveforms however suggest that this exactly the case. Please clarify about the connected load and control scheme for both bridge sides.

The other glitches on the waveform are needing explanation. Are you operating the H bridge with phase shift respectively unipolar modulation, so the glitches are representing the other side of the bridge?

Reverse recovery would play a role if you have load current in the "passive" quadrants. Do you?

To determine the origin of losses you would want to observe load current together with the voltage switching waveform in higher resolution.
 

Yes, you need to describe the loading under your test conditions. This includes the AC output filter itself, which can still draw current even when there's no real load on its output.

With 1us of dead time, cross conduction shouldn't be an issue. You should probably try and decrease the dead time a bit, that would probably help efficiency somewhat. The effects of diode reverse recovery will only show up if the diodes are allowed to conduct in the first place. And that will depend on what the complex impedance of your load is.
 
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    sabu31

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Hi


@fvm
The loading in both 50% and 90% duty ratio is 216 ohms ,the dc link voltage being 400. I am posting the waveforms, the load current waveform is not square wave (dont know why). I have used LEM LA55-P current sensor.
I am using complementary pwm scheme given in texas 28335 microcontroller, with active high complementary



@mtwieg

The above mentioned inverter is also used in sine-pwm mode with an L-C filter connected to it. In this sine pwm ,diodes of one diagonal will conduct during one half cycle of pwm
 

Hi all

any ideas to solve the problem...or any starting leads or references?

Thankyou.
 

The load seems to be RL and the assumption about different load current in both operation points has turned out right.
With 90% duty cycle, the current is higher and one switching edge is involving substrate diode reverse recovery. Thus mtwieg's suggestion from post #15 can most likely help to reduce switching losses.

But you didn't yet give information about the loss extent, e.g. estimated power dissipation. So we don't know if it's excessive or rather normal operation.
 

sabu31 said:
Hi


@fvm
The loading in both 50% and 90% duty ratio is 216 ohms ,the dc link voltage being 400. I am posting the waveforms, the load current waveform is not square wave (dont know why). I have used LEM LA55-P current sensor.
I am using complementary pwm scheme given in texas 28335 microcontroller, with active high complementary



@mtwieg

The above mentioned inverter is also used in sine-pwm mode with an L-C filter connected to it. In this sine pwm ,diodes of one diagonal will conduct during one half cycle of pwm
Click to expand...
When you say the load is 216ohms, is that after the LC filter, or is the resistive load connected directly to the bridge outputs? From the shape of the current waveforms, I'm assuming that you are still using the LC filter. That means that the bridge diodes will conduct current during the dead time, which may contribute to heating. As FvM stated above, finding out if your dissipation is extraordinary or not requires that you give specific information about the load (including any LC filters used), and how the FETs are cooled (we'll want an estimate of thermal impedance to ambient, and a rough estimate of the case temperature). You might as well post a decent schematic as well.

Also in the third waveform above, I'm wondering what the cause of the spike in the current trace in between the switching transitions is.
 
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    sabu31

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Tahmid said:
One possibility is that, at higher duty cycles, the MOSFET is not being fully turned on. You may need to use a larger bootstrap capacitor. What is the value of the bootstrap capacitor you are using now?
Click to expand...

Hi sabu,
Tahmid is absolutely right
case1. there is a train of pulses in one half cycle for spwm
case2. there is only one pulse per halfcycle

in case1 refresh chaging of the bootstap capacitor charging willnot takeplace until the other arm of H bridge is charged. hence the charge may not be sufficient for the last pulses of the train hence the heat because on the last portion FET will not be fully swithed on
in case2 refresh chaging of the bootstap capacitor take place on alternate pulses so no heat.
If you find this helpfull dont forget to click the helpedme button
regards ani
 
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