what does a decap cell contain ?

What does layout of a decap cell contain inside. how do they work . Please explain

A decoupling capacitor is a capacitor used to decouple one part of an electrical network (circuit) from another. Noise caused by other circuit elements is shunted through the capacitor, reducing the effect they have on the rest of the circuit.
For example, if the voltage level for a device is fixed, changing power demands are manifested as changing current demand. The power supply must accommodate these variations in current draw with as little change as possible in the power supply voltage. When the current draw in a device changes, the power supply cannot respond to that change instantaneously. As a consequence, the voltage at the device changes for a brief period before the power supply responds. The voltage regulator adjusts the amount of current it is supplying to keep the output voltage constant but can only effectively maintain the output voltage for events at frequencies from DC to a few hundred kHz, depending on the regulator (some are effective at regulating in the low MHz). For transient events that occur at frequencies above this range, there is a time lag before the voltage regulator responds to the new current demand level.
This is where the decoupling capacitor comes in. The decoupling capacitor works as the device’s local energy storage. The capacitor cannot provide DC power because it stores only a small amount of energy but this energy can respond very quickly to changing current demands. The capacitors effectively maintain power-supply voltage at frequencies from hundreds of kHz to hundreds of MHz (in the milliseconds to nanoseconds range). Decoupling capacitors are not useful for events occurring above or below this range.

vivekrajeev said:

What does layout of a decap cell contain inside. how do they work . Please explain

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It is a simple n or p device with poly connected to VDD and Source and Drain connected to VSS with appropriate wells.

hos does a poly connected to VDD and source /drain connected to VSS work as decap

Vivek,
We are forming a capacitor by having different potential between gate and source/drain. The cap is fully charged initially and supplies charge when some logic draws high current suddenly. So you are reducing the IR drop.

thanks i opened the layout and i find the same. CPO is contact for poly right ?? poly is connected to VSS in this so it forms a gate type decap where the upper plate is POLY and lower is lower is BULK. am i right ??

yes you got it right. It is basicaly used for IR drop reduction and thereby also filling up your empty areas.