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CMOS current limiter

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Junus2012

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Dear friends

I am designing CMOS adaptive biasing operational amplifier, this technique is providing a dynamic bias current that increase as the input increase, the circuit that I designed is providing this increment attentionally so at a little high input the bias current is going to be very large and more than what I need.

The solution is that I should have like a current limiter circuit at the bias terminal that would allow the accepted value to pass and limit the maximum value for what ever the input value and I need your suggestions for this circuit.

Thank you all

Regards
 

It would help if you show your bias circuit!
 

Hi,
One can use digital control on regulating the bias current by using parallel current sources.
Basic comparator to compare the input signal, compare with reference and turn on/off the biasing legs.
One can also add/remove the input differential pair, like one does to get rail to rail input range.
However this will add non-linearity into the system, but can be used for IO kind of circuits, where monotonicity is more important than avoiding non-linearity.

Hope this helps.

Supreet
 

Hi,
One can use digital control on regulating the bias current by using parallel current sources.
Basic comparator to compare the input signal, compare with reference and turn on/off the biasing legs.
One can also add/remove the input differential pair, like one does to get rail to rail input range.
However this will add non-linearity into the system, but can be used for IO kind of circuits, where monotonicity is more important than avoiding non-linearity.

Hope this helps.

Supreet


one question won't it imply that if current is higher literally no current flow from the op of the comparator this means more off time and can it be resolved
 

Dear All
Thank you for your participation on my topic

Actually I have tried before to control the bias current digitally but not with turning it on and off. what I did , I used a MUX circuit to pass Io or Io/4 , so I have one source of Io and I mirrored it in other branch with factor of 1/4. but the drowback of this technique is that the current can increase of factor of 4 before the circuit can reduce it
Regards
 

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