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[RTL]Wait statement in RTL

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Normal RTL in this context is behavioural Code.
All behavioural code is not synthesizable.
 

What do you mean by normal RTL?
Simulators understand wait statements where as synthesis tools does not.
 

The VHDL could be used to code the test bench and the wait statement is usefull. When the VHDL code is used to be synthesize for a flag or ASIC, wait statement must not be used, or could not be transform into logic.
 

dftrtl said:
What do you mean by normal RTL?
Simulators understand wait statements where as synthesis tools does not.
Click to expand...

I know that the RTL is always synthesizable.
But see the linkhttps://www.edaboard.com/threads/265918/
In this link Dave_59 sir told that We can write the RTL which is not always synthesizable.SO I am little bit confusing.
 

@Dave: Can me please tell me the tools that support wait statement for synthesis.
 

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