Question About A Single Clock Implementation Of MIPS

I have watched the book "Computer Organization And Design", and i want to implement a simple single clock mips(chapter 4.4) in my altera fpga board. Here is the problem i encountered:
the altera fpga sram read the address at the rising edge and gives the valid data the next clock rising edge. that seems make the single clock implementation impossible, because the Load from memory seems impossible to finish in one cycle.

new to this area, i don't know if i am correct about this,and if my understanding is alright , what can i do to implement this single cycle mips?

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i figured it out , using a asyn_memory that can finish the read in single clock can solve the problem.
now i am using the negedge to read out the data , and i think it will makes the timing a little tight , what kind of sram or cache the real MIPS are using ?

why load from memory can not be finished in one cycle?

the previous sram i am using cannot finish a read operation in a single clock (it read the addr at the first clock rising edge and then output the valid data at the next clock rising edge).instead i used a asyn memory that can finish the read operation in one clock cycle(it read the addr at the rising edge and then output the valid data at the following falling edge,thus,finish the read in one clock cycle)

i don't know if i am well explained , if not reply me with you questions

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lpeter said:

why load from memory can not be finished in one cycle?

Click to expand...

the previous sram i am using cannot finish a read operation in a single clock (it read the addr at the first clock rising edge and then output the valid data at the next clock rising edge).instead i used a asyn memory that can finish the read operation in one clock cycle(it read the addr at the rising edge and then output the valid data at the following falling edge,thus,finish the read in one clock cycle)

i don't know if i am well explained , if not reply me with you questions