DC Link capacitor/filter for single phase inverter

I am building a H-bridge DC-AC inverter to test the efficiency of new MOSFETs



I now need to design the actual input filter/capacitor. I know this is required in order to remove the harsh current/voltage spikes that the power supply won't be able to handle. But how do I go about defining values? I know I will need a capacitor in parallel and possibly a resistor/inductor in series.

I will measure the input power by measuring the voltage across the capacitor and the current through the inductor/resistor. I will then put the system in a calorimeter to measure the power loss and hence efficiency.

My Dc-Link voltage will be around 750V, and output current through the load will be around 15A RMS @ 50Hz - the switching frequency will be varied from 2.5kHz up to 10-15kHz

I would of thought the caps are to reduce ripple. It would be pointless to synthesize AC with PWM if the pulse levels werent at consisten amplitude

Yes so the DC voltage is constantly at close to 750V?

It depends on what the DC voltage is being generated from. Bridge rectifier, DC-DC converter, PFC frontend, etc.

For a 50 Hz inverter as apparently intended, a minimum bus capacitor size will be also set by the 100 Hz load modulation, assumed you don't want to pass the 100 Hz ripple to the input source. That's an essential difference to a 3-phase inverter that consumes constant instantaneous power with sine output. You get the minimum required capacitance by specifying a maximum DC bus voltage ripple.

Besides low frequent ripple, the bus capcitors have to buffer PWM frequent ripple. It's usually smaller than the load current, depending on the output inductance. But to avoid inductive overvoltages, you'll possibly want low inductance "snubber" capacitors near to the output bridge, e.g. polypropylene foil capacitors.

IMHO the calorimeter setup is unnecessary complicated (and probably not very accurate). Electrical measurements of in- and output power will usually give better accuracy in efficiency determination. Besides transistor performance, actual efficiency will depend very much on gate waveform optimization.

But the efficiency of these MOSFETs is expected to be over 99%. What I will do is put the whole system in a calorimeter, calculate the overall power loss, and then I will characterise the inductor on its own inside the calorimeter, so that I can then subtract the losses due to the inductor - and get the losses just for the MOSFETs.

Getting the switching losses etc is going to be beyond my ability at this moment in time, a 2ns propagation delay that outsincs the voltage or current measurements basically destroys the accuracy.

What do you mean by the 100Hz load modulation? The inductor is literally just there to draw a particular current through the MOSFETs, the set up is supposed to attempt to emulate one leg of a wind turbine converter.

I am trying different sizes for the capacitor in LTSpice but it just seems that I might as well take a random large one and be done with it rather than wasting time being specific about it?

What do you mean by the 100Hz load modulation? The inductor is literally just there to draw a particular current through the MOSFETs, the set up is supposed to attempt to emulate one leg of a wind turbine converter.

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See post #1. You said to apply 50 Hz output current and a RL load. In case of a pure L load, there will be a´much lower output power, but still 100 Hz DC bus ripple according to the 50 Hz AC output current.

FvM said:

See post #1. You said to apply 50 Hz output current and a RL load. In case of a pure L load, there will be a´much lower output power, but still 100 Hz DC bus ripple according to the 50 Hz AC output current.

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I don't understand this, my load is just purely an inductor. Why is there going to be a 100Hz DC bus ripple? Why wouldn't it be more related to the switching frequency?

If you source/sink reactive power from/to the bridge output, you will get an AC current of double frequency in the bus capacitors and respective voltage ripple. But it depends on the load inductance respectively apparent power level.