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Error (10515): VHDL type mismatch error

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Aya2002

Aya2002

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Dear Friends,

Kindly, I just started with VHDL, I need to display the numbers in the 7 segment display, I do not know how to solve this problem, I have an integer input and I need to display it. Always I face this message of error: (Error (10515): VHDL type mismatch error at ssd.vhd(18): bit type does not match string literal). would somebody help me please?
Thank you

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity ssd is
port (da0, da1 : IN STD_LOGIC;
clk, reset : IN STD_LOGIC;
a0, b0, c0, d0, e0, f0, g0 : OUT bit;
a1, b1, c1, d1, e1, f1, g1 : OUT bit);
end ssd;
ARCHITECTURE dis OF ssd IS
BEGIN
PROCESS(clk, reset)
VARIABLE da0: INTEGER RANGE 0 TO 10;
VARIABLE da1: INTEGER RANGE 0 TO 10;
BEGIN
-- ---- --------
CASE da0 IS
WHEN 0 => a0 <= "0";
b0 <= "0";
c0 <= "0";
d0 <= "0";
e0 <= "0";
f0 <= "0";
g0 <= "1";
WHEN 1 => a0 <= "1";
b0 <= "0";
c0 <= "0";
d0 <= "1";
e0 <= "1";
f0 <= "1";
g0 <= "1";
WHEN 2 => a0 <= "0";
b0 <= "0";
c0 <= "1";
d0 <= "0";
e0 <= "0";
f0 <= "1";
g0 <= "0";
WHEN 3 => a0 <= "0";
b0 <= "0";
c0 <= "0";
d0 <= "0";
e0 <= "1";
f0 <= "1";
g0 <= "0";
WHEN 4 => a0 <= "1";
b0 <= "0";
c0 <= "0";
d0 <= "1";
e0 <= "1";
f0 <= "0";
g0 <= "0";
WHEN 5 => a0 <= "0";
b0 <= "1";
c0 <= "0";
d0 <= "0";
e0 <= "1";
f0 <= "0";
g0 <= "0";
WHEN 6 => a0 <= "0";
b0 <= "1";
c0 <= "0";
d0 <= "0";
e0 <= "0";
f0 <= "0";
g0 <= "0";
WHEN 7 => a0 <= "0";
b0 <= "0";
c0 <= "0";
d0 <= "1";
e0 <= "1";
f0 <= "1";
g0 <= "1";
WHEN 8 => a0 <= "0";
b0 <= "0";
c0 <= "0";
d0 <= "0";
e0 <= "0";
f0 <= "0";
g0 <= "0";
WHEN 9 => a0 <= "0";
b0 <= "0";
c0 <= "0";
d0 <= "0";
e0 <= "1";
f0 <= "0";
g0 <= "0";
WHEN OTHERS => a0 <= "0";
b0 <= "1";
c0 <= "0";
d0 <= "0";
e0 <= "0";
f0 <= "0";
g0 <= "0";

CASE da1 IS
WHEN 0 => a1 <= "0";
b1 <= "0";
c1 <= "0";
d1 <= "0";
e1 <= "0";
f1 <= "0";
g1 <= "1";
WHEN 1 => a1 <= "1";
b1 <= "0";
c1 <= "0";
d1 <= "1";
e1 <= "1";
f1 <= "1";
g1 <= "1";
WHEN 2 => a1 <= "0";
b1 <= "0";
c1 <= "1";
d1 <= "0";
e1 <= "0";
f1 <= "1";
g1 <= "0";
WHEN 3 => a1 <= "0";
b1 <= "0";
c1 <= "0";
d1 <= "0";
e1 <= "1";
f1 <= "1";
g1 <= "0";
WHEN 4 => a1 <= "1";
b1 <= "0";
c1 <= "0";
d1 <= "1";
e1 <= "1";
f1 <= "0";
g1 <= "0";
WHEN 5 => a1 <= "0";
b1 <= "1";
c1 <= "0";
d1 <= "0";
e1 <= "1";
f1 <= "0";
g1 <= "0";
WHEN 6 => a1 <= "0";
b1 <= "1";
c1 <= "0";
d1 <= "0";
e1 <= "0";
f1 <= "0";
g1 <= "0";
WHEN 7 => a1 <= "0";
b1 <= "0";
c1 <= "0";
d1 <= "1";
e1 <= "1";
f1 <= "1";
g1 <= "1";
WHEN 8 => a1 <= "0";
b1 <= "0";
c1 <= "0";
d1 <= "0";
e1 <= "0";
f1 <= "0";
g1 <= "0";
WHEN 9 => a1 <= "0";
b1 <= "0";
c1 <= "0";
d1 <= "0";
e1 <= "1";
f1 <= "0";
g1 <= "0";
WHEN OTHERS => a1 <= "0";
b1 <= "1";
c1 <= "0";
d1 <= "0";
e1 <= "0";
f1 <= "0";
g1 <= "0";
END CASE;
end process;
end dis;
 

Bit constants have single quotes, string respectively vector constants double quotes. It's wrong in all assignments.

You have also da0 and da1 defined as std_logic and integer variable at the same time.
 
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    Aya2002

    Aya2002

    Points: 2
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thank you FvM, I tried all the cases but still with the same problem. Please, help me, I am very sad...

please write down here what should I write, give me an example
 

I tried all the cases but still with the same problem
Click to expand...
It's not true. If you change all '0' and '1' bit constants to the right syntax, and supplement a missing END CASE, you get warnings instead:
Code: 
Warning (10543): VHDL Variable Declaration warning at ssd.vhd(13): used default initial value for variable "da0" because variable was never assigned a value or an initial value expression. Use of default initial value may introduce unintended design optimizations.
They are referring to the other problem mentioned in my post.

P.S.: The simplest solution to the other problem is to change the port definition and delete the variables.
Code: 
port (da0, da1 : INTEGER RANGE 0 TO 10;

If you special requirements for the type of the port signals, you can think about it later.
 
Last edited:
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    Aya2002

    Aya2002

    Points: 2
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the end case is already written

- - - Updated - - -

I solved the problem according to your guidance. Thank you very much. Now I have another problem, before showing the problem, I will put the code here for others to make use of it. After the code below, I will tell you what was the problem.

LIBRARY ieee;
USE ieee.std_logic_1164.all;

entity ssd is
port (da0, da1 : IN integer;
clk, reset : IN STD_LOGIC;
a0, b0, c0, d0, e0, f0, g0 : OUT bit;
a1, b1, c1, d1, e1, f1, g1 : OUT bit);
end ssd;
ARCHITECTURE dis OF ssd IS
BEGIN
PROCESS(clk, reset)
-- VARIABLE da0: INTEGER RANGE 0 TO 10;
-- VARIABLE da1: INTEGER RANGE 0 TO 10;
BEGIN
-- ---- BCD to SSD conversion: --------
CASE da0 IS

WHEN 0 =>
a0 <= '0';
b0 <= '0';
c0 <= '0';
d0 <= '0';
e0 <= '0';
f0 <= '0';
g0 <= '1';
WHEN 1 => a0 <= '1';
b0 <= '0';
c0 <= '0';
d0 <= '1';
e0 <= '1';
f0 <= '1';
g0 <= '1';
WHEN 2 => a0 <= '0';
b0 <= '0';
c0 <= '1';
d0 <= '0';
e0 <= '0';
f0 <= '1';
g0 <= '0';
WHEN 3 => a0 <= '0';
b0 <= '0';
c0 <= '0';
d0 <= '0';
e0 <= '1';
f0 <= '1';
g0 <= '0';
WHEN 4 => a0 <= '1';
b0 <= '0';
c0 <= '0';
d0 <= '1';
e0 <= '1';
f0 <= '0';
g0 <= '0';
WHEN 5 => a0 <= '0';
b0 <= '1';
c0 <= '0';
d0 <= '0';
e0 <= '1';
f0 <= '0';
g0 <= '0';
WHEN 6 => a0 <= '0';
b0 <= '1';
c0 <= '0';
d0 <= '0';
e0 <= '0';
f0 <= '0';
g0 <= '0';
WHEN 7 => a0 <= '0';
b0 <= '0';
c0 <= '0';
d0 <= '1';
e0 <= '1';
f0 <= '1';
g0 <= '1';
WHEN 8 => a0 <= '0';
b0 <= '0';
c0 <= '0';
d0 <= '0';
e0 <= '0';
f0 <= '0';
g0 <= '0';
WHEN 9 => a0 <= '0';
b0 <= '0';
c0 <= '0';
d0 <= '0';
e0 <= '0';
f0 <= '0';
g0 <= '0';
WHEN OTHERS => a0 <= '1';
b0 <= '1';
c0 <= '1';
d0 <= '1';
e0 <= '1';
f0 <= '1';
g0 <= '1';
END CASE;
CASE da1 IS
WHEN 0 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '0';
e1 <= '0';
f1 <= '0';
g1 <= '1';
WHEN 1 => a1 <= '1'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '1';
e1 <= '1';
f1 <= '1';
g1 <= '1';
WHEN 2 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '1';
d1 <= '0';
e1 <= '0';
f1 <= '1';
g1 <= '0';
WHEN 3 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '0';
e1 <= '1';
f1 <= '1';
g1 <= '0';
WHEN 4 => a1 <= '1'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '1';
e1 <= '1';
f1 <= '0';
g1 <= '0';
WHEN 5 => a1 <= '0'; --7E
b1 <= '1';
c1 <= '0';
d1 <= '0';
e1 <= '1';
f1 <= '0';
g1 <= '0';
WHEN 6 => a1 <= '0'; --7E
b1 <= '1';
c1 <= '0';
d1 <= '0';
e1 <= '0';
f1 <= '0';
g1 <= '0';
WHEN 7 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '1';
e1 <= '1';
f1 <= '1';
g1 <= '1';
WHEN 8 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '0';
e1 <= '0';
f1 <= '0';
g1 <= '0';
WHEN 9 => a1 <= '0'; --7E
b1 <= '0';
c1 <= '0';
d1 <= '0';
e1 <= '1';
f1 <= '0';
g1 <= '0';
WHEN OTHERS => a1 <= '1'; --7E
b1 <= '1';
c1 <= '1';
d1 <= '1';
e1 <= '1';
f1 <= '1';
g1 <= '1';
END CASE;
end process;
end dis;

now, my problem is that, I converted the code to a symbol ( I am using Quartus II), and it is successfully converted but when I connected it to my other parts I got the following error: Error: Port "da0[31..0]" of type ssd of instance "Int_to_7_seg_disp" is missing source signal

see the attached pic.
myclock.png

would you please help me to solve this problem if you can? Thank you very much
 

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