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verilog coding style:IF,ELSE VS case?

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xiongdh

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How about this two coding style:
Style 1:
assign int_sfr_data_in = (dmem_sfr_cs == 1) ? dmem_sfr_dout :
(cmem_sfr_cs == 1) ? cmem_sfr_dout :
(dma_sfr_cs == 1) ? dma_sfr_dout :
(sec_sfr_cs == 1) ? sec_sfr_dout :
(expi_sfr_cs == 1) ? expi_sfr_dout :
evti_sfr_dout ;
/////////////////////////////////////////////////////////////////
Style 2:
case ({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs})
5'b00001 : int_sfr_data_in = dmem_sfr_dout;
5'b00010 : int_sfr_data_in = cmem_sfr_dout;
5'b00100 : int_sfr_data_in = dma_sfr_dout;
5'b01000 : int_sfr_data_in = sec_sfr_dout;
5'b10000 : int_sfr_data_in = expi_sfr_dout;
default : int_sfr_data_in = else_out;
endcase
//////////////////////////////////////////////////////////
The condition is not allowed that More than one control signal of expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs is '1' at the same time.
////////////////////////////////////////////
Please give me some remark on this two coding style on timing and area.
thanks.
 

Style two is a better way for faster speed, more readable.
 

first one will synthesised to priority encoder and second code to MUX... for timing you better stick to the second coding style.
 

These two styles are equivalent if you don't give extra synthesis directive (like //synopsys parallel_case). Keep in mind, "case" statement has priority! And the first style does not always infer priority encoder. The tool is smart enough to recognize exclusive conditions and automatically infer a MUX. For example,

assign out = (sel==2'b00) ? a : (sel==2'b01) ? b : (sel==2'b10) ? c : (sel==2'b11) ? d : 'x;

Note the 'x in the default branch can help propogate X, which is a good coding style.

It is recommended that use if statement to infer priority encoder.

Above is base on synopsys DC, different tools may have different results.
 

Style-1 is used for Wire but Style-2 is used for Register. In general Style-2 is more reliable for timing consideration. However, there are some cases of design that need direct wire output such as code interpreter. In some critical design, Style-1 got higher respond time than Style-2. One of the example to show the efficient of Style-1 is Nios-II design. At the last part of cpu.v can obviously seen the stack of code interpreter by using Style-1 for performance enhancement purpose. Instead, the old version of Nios such as Nios 3.1 is using Style-2 as the code interpreter.
 

The Style 2 cost more area and timing.even if i use //synopsys parallel_case full_case directive.But if i write like the followed and synthesis with directive.it cost area the same as style 1 ,less timing than style 1.Why????
case({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs}) //synopsys parallel_case full_case
5'b00001 : int_sfr_data_in = dmem_sfr_dout ;
5'b00010 : int_sfr_data_in = cmem_sfr_dout ;
5'b00100 : int_sfr_data_in = dma_sfr_dout ;
5'b01000 : int_sfr_data_in = sec_sfr_dout ;
5'b10000 : int_sfr_data_in = expi_sfr_dout ;
5'b00000 : int_sfr_data_in = else_out;
endcase
 

Try this sytle :
casex ({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs})
5'bxxxx1 : int_sfr_data_in = dmem_sfr_dout;
5'bxxx1x : int_sfr_data_in = cmem_sfr_dout;
5'bxx1xx : int_sfr_data_in = dma_sfr_dout;
5'bx1xxx : int_sfr_data_in = sec_sfr_dout;
5'b1xxxx : int_sfr_data_in = expi_sfr_dout;
default : int_sfr_data_in = else_out;
endcase
 

Those two style don't equal in logic
xiongdh said:
How about this two coding style:
Style 1:
assign int_sfr_data_in = (dmem_sfr_cs == 1) ? dmem_sfr_dout :
(cmem_sfr_cs == 1) ? cmem_sfr_dout :
(dma_sfr_cs == 1) ? dma_sfr_dout :
(sec_sfr_cs == 1) ? sec_sfr_dout :
(expi_sfr_cs == 1) ? expi_sfr_dout :
evti_sfr_dout ;
/////////////////////////////////////////////////////////////////
Style 2:
case ({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs})
5'b00001 : int_sfr_data_in = dmem_sfr_dout;
5'b00010 : int_sfr_data_in = cmem_sfr_dout;
5'b00100 : int_sfr_data_in = dma_sfr_dout;
5'b01000 : int_sfr_data_in = sec_sfr_dout;
5'b10000 : int_sfr_data_in = expi_sfr_dout;
default : int_sfr_data_in = else_out;
endcase
//////////////////////////////////////////////////////////
The condition is not allowed that More than one control signal of expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs is '1' at the same time.
////////////////////////////////////////////
Please give me some remark on this two coding style on timing and area.
thanks.
Click to expand...
 

Sorry for the misleading. I didn't carefully looking at your code. Style 2 will cost more because the tool will infer a 32to1 mux. Heartfree's solution will be equalivent to style 1 but is not a good coding practice (avoid casex if possible). Your modified version of style 2 will not infer a mux (the full_case directive actully adds don't care outputs as the default branch), this leads to better optimization result. The best way for coding one-hot mux is and-or combinational logic.

dout = {`width{a}} & a_out |
{`width{b}} & b_out |
...

This will not infer priority logic, if you want to priority, use if/else.
 

casex ({expi_sfr_cs, sec_sfr_cs, dma_sfr_cs,cmem_sfr_cs, dmem_sfr_cs})
5'bxxxx1 : int_sfr_data_in = dmem_sfr_dout;
5'bxxx1x : int_sfr_data_in = cmem_sfr_dout;
5'bxx1xx : int_sfr_data_in = dma_sfr_dout;
5'bx1xxx : int_sfr_data_in = sec_sfr_dout;
5'b1xxxx : int_sfr_data_in = expi_sfr_dout;
default : int_sfr_data_in = else_out;
endcase

this will be similar
assign int_sfr_data_in = (dmem_sfr_cs == 1) ? dmem_sfr_dout :
(cmem_sfr_cs == 1) ? cmem_sfr_dout :
(dma_sfr_cs == 1) ? dma_sfr_dout :
(sec_sfr_cs == 1) ? sec_sfr_dout :
(expi_sfr_cs == 1) ? expi_sfr_dout :
evti_sfr_dout ;
 

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