Single ended lvds-tx output impedance

Hi,

What is the significance of single ended DC impedance in Lvds tx?
The way it is measured in IEEE specification further complicates the understanding.

It looks like, the outputs are tied in the normal operation range of common mode and difference of voltage on the single ended output node is considered. This can be done as voltage difference/current on each outputs.

Anybody know what is the significance and why its measured like that?

-Rag

What is the significance of single ended DC impedance in Lvds tx?
The way it is measured in IEEE specification further complicates the understanding.

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The purpose of a defined "single ended" output impedance isn't founded in IEEE 1596 as far as I'm aware of.

The measurement setup suggests, that the parameter of interest is common mode output impedance. If you only refer to parameters tested in the measurement and other DC specifications, the differential output mode impedance can be varied over a wide range and still keep the specification. This would allow for different implementations like buffer with resistive divider, buffer with low drive strength and differential current source with common mode feed back.

You can also read single ended output impedance as strict specification that defines differential impedance, too. (With a range of 80 to 280 ohm)

Drivers designed according to TIA/EIA LVDS specification have often current source outputs. They won't keep the strict interpretation of single ended output impedance and possibly the comon mode impedance specification neither.

FvM said:

The purpose of a defined "single ended" output impedance isn't founded in IEEE 1596 as far as I'm aware of.

The measurement setup suggests, that the parameter of interest is common mode output impedance.
You can also read single ended output impedance as strict specification that defines differential impedance, too. (With a range of 80 to 280 ohm)

Drivers designed according to TIA/EIA LVDS specification have often current source outputs. They won't keep the strict interpretation of single ended output impedance and possibly the comon mode impedance specification neither.

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1.But measurement setup is also tricky. If common mode impedance is required, we can just do V/I. But specification is in terms of voltage difference of outputs at two different common mode voltages. !?
2.Agreed that current source outputs don't meet this specification. But in that case why IEEE would suggest such a spec with less significance?

But measurement setup is also tricky. If common mode impedance is required, we can just do V/I. But specification is in terms of voltage difference of outputs at two different common mode voltages.

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As defined, the measurement asseses only common mode impedance, not differential impedance. But as with most standards, I don't see much sense in considering why. In many cases, the most likely conclusion is that nobody in or outside the respective workgroup didn't yet complain about obvious gaps and ambiguities.

More generally, how to discuss the reasons behind a standard specification that isn't explicitely substantiated?

Only concern was to understand the spec clearly, so that design well optimized. And there are architectures not meeting this spec. So, when to meet this spec and when not to, can be understood if spec is understood.
I feel there is some reason behind using two different common mode voltages.!

I feel there is some reason behind using two different common mode voltages.!

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Yes, but not very specific, I think. The output impedance is measured with a regular termination and a voltage range according to the regular signal level, in case the driver acts non-linear.